74LVX374
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 160MHz (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX374M
T&R
74LVX374MTR
74LVX374TTR
DESCRIPTION
The 74LVX374 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE). On
the positive transition of the clock, the Q outputs
will be set to the logic state that were setup at the
PIN CONNECTION AND IEC LOGIC SYMBOLS
D inputs. While the (OE) input is low, the 8 outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state. The output control does not
affect the internal operation of flip flops; that is,
the old data can be retained or the new data can
be entered even while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/10
74LVX374
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
T
A
= 25°C
Min.
Typ.
0.3
-0.8
C
L
= 50 pF
2.0
-0.3
V
Max.
0.8
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
3.3
3.3
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
2.7
3.3
(*)
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
2.7
2.7
3.3
(*)
t
PLZ
t
PHZ
t
W
t
S
t
h
f
MAX
Output Disable
Time
CK pulse Width,
HIGH
3.3
(*)
2.7
3.3
(*)
2.7
C
L
(pF)
15
50
15
50
15
50
15
50
50
50
50
50
50
50
50
50
15
50
15
50
50
50
60
45
100
60
115
60
160
95
0.5
0.5
1.0
1.0
T
A
= 25°C
Min.
Typ.
8.5
11.0
6.7
9.2
7.6
10.1
5.9
8.4
11.5
9.6
Max.
16.3
19.8
10.6
14.1
14.5
18.0
9.3
12.8
18.5
13.2
7.5
5.0
6.5
4.5
2.0
2.0
50
40
85
55
1.5
1.5
Value
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
19.5
23.0
12.5
16.0
17.5
21.0
11.0
14.5
22.0
15.0
8.0
5.5
6.5
4.5
2.0
2.0
45
35
75
50
1.5
1.5
ns
MHz
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
20.5
24.0
13.5
17.0
18.5
22.0
12.0
15.5
23.0
16.0
8.0
5.5
6.5
4.5
2.0
2.0
ns
ns
ns
ns
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
CK to Q
3.3
(*)
Setup Time D to CK 2.7
HIGH or LOW
3.3
(*)
2.7
Hold Time D to CK
HIGH or LOW
3.3
(*)
Maximum Clock
Frequency
2.7
2.7
3.3
(*)
Output to Output
Skew Time (note
1,2)
3.3
(*)
2.7
3.3
(*)
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
4/10
传感器
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