74LVQ280
9 BIT PARITY GENERATOR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 8 ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2µA(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ280MTR
74LVQ280TTR
DESCRIPTION
The 74LVQ280 is a low voltage CMOS 9 BIT
PARITY GENERATOR fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low noise
3.3V applications.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (ΣODD and
ΣEVEN).
The nine
Figure 1: Pin Connection And IEC Logic Symbols
data inputs control the output conditions. When
the number of high level input is odd,
ΣODD
output is kept high and
ΣEVEN
output low.
Conversely, when the number of high level is
even,
ΣEVEN
output is kept high and
ΣODD
low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easily expanded by cascading.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2004
Rev. 2
1/11
74LVQ280
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
5
6
8, 9, 10, 11,
12, 13, 1, 2,
4
3
7
14
SYMBOL
ΣEVEN
ΣODD
A to I
NAME AND FUNCTION
Even Parity Output
Odd Parity Output
Data Inputs
NC
GND
V
CC
No Connection
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
OUTPUTS
NUMBER OF INPUTS A - I THAT ARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
ΣEVEN
H
L
ΣODD
L
H
Figure 3: Logic Diagram
2/11
74LVQ280
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
300
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Parameter
Value
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
Unit
V
V
V
°C
1) Truth Table guaranteed: 1.2V to 3.6V
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
2.0
0.8
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
V
OL
Low Level Output
Voltage
I
O
=50
µA
3.0
I
O
=12 mA
I
O
=24 mA
I
I
I
CC
I
OLD
I
OHD
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
±
0.1
2
36
-25
0.002
0
0.1
0.36
2.9
2.58
2.99
2.9
2.48
2.2
0.1
0.44
0.55
±
1
20
25
-25
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
0.1
0.44
0.55
±
1
20
µA
µA
mA
mA
V
V
Max.
-55 to 125°C
Min.
2.0
0.8
Max.
V
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/11
74LVQ280
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
C
L
= 50 pF
3.3
0.8
V
T
A
= 25°C
Min.
Typ.
0.3
-0.8
2
-0.3
Max.
0.8
V
V
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
2.7
(*)
Value
T
A
= 25°C
Min.
Typ.
9.9
8.0
0.5
0.5
Max.
16.0
11.5
1.0
1.0
-40 to 85°C
Min.
Max.
19.0
13.5
1.0
1.0
-55 to 125°C
Min.
Max.
22.0
16.0
1.0
1.0
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
t
OSLH
t
OSHL
Output To Output
Skew Time
(note1, 2)
3.3
(*)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
59
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
4/11
74LVQ280
Figure 4: Test Circuit
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
Figure 5: Waveform - Propagation Delays
(f=1MHz; 50% duty cycle)
5/11
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
