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74LCX373

OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

s

5V TOLERANT INPUTS AND OUTPUTS

HIGH SPEED :

t

PD

= 8.0 ns (MAX.) at V

CC

= 3V

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I

OH

| = I

OL

= 24mA (MIN) at V

CC

= 3V

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

t

PLH

≅

t

PHL

OPERATING VOLTAGE RANGE:

V

CC

(OPR) = 2.0V to 3.6V (1.5V Data

Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

SOP

TSSOP

ORDER CODES

PACKAGE

SOP

TSSOP

TUBE

74LCX373M

T&R

74LCX373MTR

74LCX373TTR

DESCRIPTION

The 74LCX373 is a low voltage CMOS OCTAL

D-TYPE LATCH with 3 STATE OUTPUT

NON-INVERTING fabricated with sub-micron

silicon gate and double-layer metal wiring C

2

MOS

technology. It is ideal for low power and high

speed 3.3V applications; it can be interfaced to 5V

signal environment for both inputs and outputs.

These 8 bit D-Type latch are controlled by a latch

PIN CONNECTION AND IEC LOGIC SYMBOLS

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input. When the LE is

taken low, the Q outputs will be latched precisely

at the logic level of D input data. While the (OE)

input is low, the 8 outputs will be in a normal logic

state (high or low logic level) and while (OE) is in

high level, the outputs will be in a high impedance

state.

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

September 2001

1/10

74LCX373

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No

1

2, 5, 6, 9, 12,

15, 16,19

3, 4, 7, 8, 13,

14, 17, 18

11

10

20

SYMBOL

OE

D0 to D7

Q0 to Q7

LE

GND

V

CC

NAME AND FUNCTION

3 State Output Enable

Input (Active LOW)

Data Inputs

3-State Outputs

Latch Enable Input

Ground (0V)

Positive Supply Voltage

TRUTH TABLE

INPUT

OE

H

L

LE

X

L

H

D

X

L

H

OUTPUT

Q

Z

NO CHANGE*

L

H

X : Don’t Care

Z : High Impedance

* : Q Outputs are latched at the time when the LE input is taken

LOW.

LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays

2/10

74LCX373

ABSOLUTE MAXIMUM RATINGS

Symbol

V

CC

V

I

V

O

V

O

I

IK

I

OK

I

O

I

CC

I

GND

T

stg

T

L

Supply Voltage

DC Input Voltage

DC Output Voltage (OFF State)

DC Output Voltage (High or Low State) (note 1)

DC Input Diode Current

DC Output Diode Current (note 2)

DC Output Current

DC Supply Current per Supply Pin

DC Ground Current per Supply Pin

Storage Temperature

Lead Temperature (10 sec)

Parameter

Value

-0.5 to +7.0

-0.5 to V

CC

+ 0.5

- 50

±

50

±

100

±

100

-65 to +150

300

Unit

V

mA

°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is

not implied

1) I

O

absolute maximum rating must be observed

2) V

O

< GND

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

V

I

V

O

V

O

I

OH

, I

OL

I

OH

, I

OL

T

op

dt/dv

Supply Voltage (note 1)

Input Voltage

Output Voltage (OFF State)

Output Voltage (High or Low State)

High or Low Level Output Current (V

CC

= 3.0 to 3.6V)

High or Low Level Output Current (V

CC

= 2.7V)

Operating Temperature

Input Rise and Fall Time (note 2)

Parameter

Value

2.0 to 3.6

0 to 5.5

0 to V

CC

±

24

±

12

-55 to 125

0 to 10

Unit

V

mA

°C

ns/V

1) Truth Table guaranteed: 1.5V to 3.6V

2) V

IN

from 0.8V to 2V at V

CC

= 3.0V

3/10

74LCX373

DC SPECIFICATIONS

Test Condition

Symbol

Parameter

V

CC

(V)

-40 to 85 °C

Min.

2.0

2.7 to 3.6

0.8

2.7 to 3.6

2.7

3.0

V

OL

Low Level Output

Voltage

2.7 to 3.6

2.7

3.0

I

off

I

OZ

Input Leakage

Current

Power Off Leakage

Current

High Impedance

Output Leakage

Current

Quiescent Supply

Current

I

CC

incr. per Input

2.7 to 3.6

0

2.7 to 3.6

I

O

=-100

µA

I

O

=-12 mA

I

O

=-18 mA

I

O

=-24 mA

I

O

=100

µA

I

O

=12 mA

I

O

=16 mA

I

O

=24 mA

V

I

= 0 to 5.5V

V

I

or V

O

= 5.5V

V

I

= V

IH

or V

IL

V

O

= 0 to V

CC

V

I

= V

CC

or GND

V

I

or V

O

= 3.6 to 5.5V

V

IH

= V

CC

- 0.6V

V

CC

-0.2

2.2

2.4

2.2

0.2

0.4

0.55

±

5

10

±

5

10

±

10

500

V

CC

-0.2

2.2

2.4

2.2

0.2

0.4

0.55

±

5

10

±

5

10

±

10

500

µA

V

0.8

V

Max.

Value

-55 to 125 °C

Min.

2.0

Max.

V

Unit

V

IH

V

IL

V

OH

High Level Input

Voltage

Low Level Input

Voltage

High Level Output

Voltage

I

CC

∆I

CC

2.7 to 3.6

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition

Symbol

Parameter

V

CC

(V)

3.3

C

L

= 50pF

V

IL

= 0V, V

IH

= 3.3V

Value

T

A

= 25 °C

Min.

Typ.

0.8

-0.8

Max.

V

Unit

V

OLP

V

OLV

Dynamic Low Level Quiet

Output (note 1)

1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is

measured in the LOW state.

4/10

74LCX373

AC ELECTRICAL CHARACTERISTICS

Test Condition

Symbol

Parameter

V

CC

(V)

2.7

3.0 to 3.6

2.7

3.0 to 3.6

2.7

3.0 to 3.6

2.7

3.0 to 3.6

2.7

3.0 to 3.6

2.7

3.0 to 3.6

2.7

3.0 to 3.6

50

500

2.5

50

500

2.5

50

500

2.5

C

L

(pF)

50

R

L

(Ω)

500

t

s

=

t

r

(ns)

2.5

-40 to 85 °C

Min.

1.5

2.5

1.5

3.3

1.0

Max.

9.0

8.0

9.5

8.5

9.5

8.5

7.5

Value

-55 to 125 °C

Min.

1.5

2.5

1.5

3.3

1.0

ns

Max.

9.0

8.0

9.5

8.5

9.5

8.5

7.5

ns

Unit

t

PLH

t

PHL

t

PLH

t

PHL

t

PZL

t

PZH

Propagation Delay

Time (Dn to Qn)

Propagation Delay

Time (LE to Qn)

Output Enable Time

to HIGH and LOW

level

Output Disable Time

from HIGH to LOW

level

Set-Up Time, HIGH

or LOW level

(Dn to LE)

Hold Time, HIGH or

LOW level

(Dn to LE)

LE Pulse Width,

HIGH

Output To Output

Skew Time (note1,

2)

t

PLZ

t

PHZ

t

S

t

h

t

W

t

OSLH

t

OSHL

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-

ing in the same direction, either HIGH or LOW (t

OSLH

= | t

PLHm

- t

PLHn

|, t

OSHL

= | t

PHLm

- t

PHLn

|)

2) Parameter guaranteed by design

CAPACITIVE CHARACTERISTICS

Test Condition

Symbol

Parameter

V

CC

(V)

3.3

V

IN

= 0 to V

CC

V

IN

= 0 to V

CC

f

IN

= 10MHz

V

IN

= 0 or V

CC

Value

T

A

= 25 °C

Min.

Typ.

6

12

50

Max.

pF

Unit

C

IN

C

OUT

C

PD

Input Capacitance

Output Capacitance

Power Dissipation Capacitance

(note 1)

1) C

PD

is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I

CC(opr)

= C

PD

x V

CC

x f

IN

+ I

CC

/8 (per latch)

5/10

74LCX373_04

74LCX373_04概述

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