74LCX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 5.4 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
PIN CONNECTION
bs
O
DESCRIPTION
The 74LCX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE) input is low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high imped-
ance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
et
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TUBE
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T&R
74LCX16373TTR
February 2003
1/10
74LCX16373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
SYMBOL
1OE
NAME AND FUNCTION
IEC LOGIC SYMBOLS
bs
O
H
L
L
L
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1LE
Latch Enable Input
4, 10, 15, 21,
GND
Ground (0V)
28, 34, 39, 45
7, 18, 31, 42
V
CC
Positive Supply Voltage
et
l
o
ro
P
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d
s)
t(
O
-
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b
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P
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t(
TRUTH TABLE
INPUTS
LE
X
L
H
H
D
X
X
L
H
OUTPUT
Q
Z
NO CHANGE *
L
H
OE
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
2/10
74LCX16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (OFF State)
DC Input Diode Current
DC Output Current
Parameter
DC Output Voltage (High or Low State) (note 1)
DC Output Diode Current (note 2)
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
b
O
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
et
l
so
V
CC
V
I
V
O
V
O
od
r
P
e
uc
s)
t(
O
-
so
b
te
le
ro
P
uc
d
s)
t(
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
RECOMMENDED OPERATING CONDITIONS
Symbol
Supply Voltage (note 1)
Input Voltage
Output Voltage (OFF State)
Output Voltage (High or Low State)
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V)
Operating Temperature
Input Rise and Fall Time (note 2)
Parameter
Value
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
°C
ns/V
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
3/10
74LCX16373
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
V
CC
(V)
-40 to 85 °C
Min.
2.0
2.7 to 3.6
0.8
2.7 to 3.6
2.7
3.0
V
OL
Low Level Output
Voltage
2.7 to 3.6
2.7
3.0
I
I
I
off
I
OZ
Input Leakage
Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
I
CC
incr. per Input
2.7 to 3.6
0
2.7 to 3.6
I
O
=-100
µA
I
O
=-12 mA
I
O
=-18 mA
I
O
=-24 mA
I
O
=100
µA
I
O
=12 mA
I
O
=16 mA
I
O
=24 mA
V
I
= 0 to 5.5V
V
I
or V
O
= 5.5V
V
I
= V
IH
or V
IL
V
O
= 0 to V
CC
V
CC
-0.2
2.2
2.4
2.2
0.2
0.4
0.4
0.55
V
CC
-0.2
2.2
2.4
2.2
0.8
V
Max.
Value
-55 to 125 °C
Min.
2.0
Max.
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
I
CC
∆I
CC
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
O
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
bs
V
OLP
V
OLV
et
l
o
ro
P
e
uc
d
V
I
or V
O
= 3.6 to 5.5V
V
IH
= V
CC
- 0.6V
2.7 to 3.6
2.7 to 3.6
s)
t(
V
I
= V
CC
or GND
O
-
s
b
te
le
o
±
5
10
r
P
d
o
uc
0.2
s)
t(
V
0.4
0.4
V
0.55
±
5
10
±
5
20
±
20
500
µA
µA
µA
µA
µA
±
5
20
±
20
500
Test Condition
V
CC
(V)
3.3
C
L
= 50pF
V
IL
= 0V, V
IH
= 3.3V
Value
T
A
= 25 °C
Min.
Typ.
0.8
-0.8
Max.
V
Unit
Parameter
Dynamic Low Level Quiet
Output (note 1)
4/10
74LCX16373
AC ELECTRICAL CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
50
50
50
500
500
500
2.5
2.5
50
500
2.5
50
500
2.5
C
L
(pF)
50
50
50
R
L
(Ω)
500
500
500
t
s
=
t
r
(ns)
2.5
2.5
2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
Max.
5.9
5.4
6.4
5.5
6.5
6.1
6.3
6.0
Value
-55 to 125 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
Max.
5.9
5.4
6.4
5.5
6.5
6.1
6.3
ns
ns
ns
Unit
t
PLH
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
Propagation Delay
Time (Dn to Qn)
Propagation Delay
Time (LE to Qn)
Output Enable Time
to HIGH and LOW
level
Output Disable Time
from HIGH to LOW
level
Set-Up Time, HIGH
or LOW level
(Dn to LE)
Hold Time, HIGH or
LOW level
(Dn to LE)
LE Pulse Width,
HIGH
Output To Output
Skew Time (note1,
2)
t
PLZ
t
PHZ
t
S
t
h
t
W
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
bs
O
C
OUT
C
PD
et
l
o
Input Capacitance
ro
P
e
uc
d
)-
(s
t
V
CC
(V)
3.3
3.3
3.3
b
O
2.5
so
te
le
1.5
3.0
3.0
1.5
ro
P
1.0
2.5
uc
d
6.0
s)
t(
ns
ns
1.5
1.5
ns
ns
1.0
ns
3.0
3.0
Test Condition
Value
T
A
= 25 °C
Min.
Typ.
7
8
20
Max.
pF
pF
pF
Unit
Parameter
V
IN
= 0 to V
CC
V
IN
= 0 to V
CC
f
IN
= 10MHz
V
IN
= 0 or V
CC
Output Capacitance
Power Dissipation Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
5/10
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