TS274
High performance CMOS quad operational amplifier
Features
■
■
■
■
■
Output voltage can swing to ground
Excellent phase margin on capacitive loads
Gain bandwidth product: 3.5 MHz
Unity gain stable
Two input offset voltage selections
SO-14
(Plastic micropackage)
DIP14
(Plastic package)
Description
The TS274 devices are low cost, quad
operational amplifiers designed to operate with
single or dual supplies. These operational
amplifiers use the ST silicon gate CMOS process
giving an excellent consumption-speed ratio.
These series are ideally suited for low
consumption applications.
Three power consumptions are available thus
offering the best consumption-speed ratio for your
application:
■
■
■
TSSOP14
(Thin shrink small outline package)
Pin connections
(top view)
Output 1 1
Inverting Input 1 2
Non-inverting Input 1 3
V
CC
+ 4
Non-inverting Input 2 5
Inverting Input 2 6
Output 2 7
+
-
+
-
-
+
-
+
14 Output 4
13 Inverting Input 4
12 Non-inverting Input 4
11 V
CC
-
10 Non-inverting Input 3
9
8
Inverting Input 3
Output 3
I
CC
= 10 µA/amp: TS27L4 (very low power)
I
CC
= 150 µA/amp: TS27M4 (low power)
I
CC
= 1 mA/amp: TS274 (standard)
These CMOS amplifiers offer very high input
impedance and extremely low input currents. The
major advantage versus JFET devices is the very
low input currents drift with temperature (see
Figure 5 on page 6).
For enhanced features of TS274, in particular rail-
to-rail capability and low offset voltage, two new
Table 1.
Part
number
TSV914
TSV994
families, TSV91x and TSV99x will better suit low
voltage applications.
Enhanced related families
V
CC
range (V)
2.5 - 5.5
2.5 - 5.5
Rail-to-
rail I/O
I/O
I/O
V
io
max
(mV)
1.5/4.5
1.5/4.5
I
ib
max
(pA)
10
10
A
vd
min
(dB)
80
80
I
CC
max
(mA)
1.1
1.1
GBP typ
(MHz)
8
20
(G
≥3)
SR typ
(V/µs)
4.5
10
Packages
SO-14,
TSSOP14
SO-14,
TSSOP14
February 2008
Rev 3
1/14
www.st.com
14
Absolute maximum ratings and operating conditions
TS274
1
Absolute maximum ratings and operating conditions
Table 2.
Symbol
V
CC+
V
id
V
in
I
o
I
in
T
oper
T
stg
Absolute maximum ratings (AMR)
Parameter
Supply voltage
(1)
Differential input voltage
(2)
Input voltage
(3)
Output current for V
CC+
≥
15V
Input current
Operating free-air temperature range
Storage temperature range
Thermal resistance junction to ambient
(4)
SO-14
TSSOP14
DIP14
Thermal resistance junction to case
SO-14
TSSOP14
DIP14
HBM: human body model
(5)
0 to +70
TS274C/AC
18
±18
-0.3 to 18
±30
±5
-40 to +125
TS274I/AI
Unit
V
V
V
mA
mA
°C
°C
-65 to +150
103
100
80
31
32
33
500
100
800
R
thja
°C/W
R
thjc
°C/W
V
V
V
ESD
MM: machine model
(6)
CDM: charged device model
(7)
1. All values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive
supply voltage.
4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
5. Human body model: A 100pF capacitor is charged to the specified voltage, then discharged through a
1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
6. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5Ω). This is done for all couples of
connected pin combinations while the other pins are floating.
7. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
Table 3.
Symbol
V
CC+
V
icm
T
oper
Operating conditions
Parameter
Supply voltage
Common mode input voltage range
Operating free-air temperature range
TS274C
TS274I
Value
3 to 16
0 to V
CC+
- 1.5
0 to 70
-40 to 125
Unit
V
V
°C
2/14
TS274
Block diagram and circuit schematics
2
Block diagram and circuit schematics
Figure 1.
Block diagram
V
CC
Current
source
xI
Input
differential
Second
stage
Output
stage
Output
V
CC
E
E
3/14
4/14
Figure 2.
V
CC
Block diagram and circuit schematics
T
24
T
25
T
26
T
6
T
8
T
27
T
5
T
10
T
15
R
2
T
28
T
1
Input
R1
C1
Input
T
2
T
11
T
12
Schematic diagram (for 1/4 TS274)
T
17
T
18
T
7
T
23
T
3
Output
T
19
T
4
T
16
T
9
T
13
T
14
T
20
T
22
T
21
T
29
V
CC
TS274
TS274
Electrical characteristics
3
Table 4.
Symbol
Electrical characteristics
V
CC+
= +10V, V
CC-
= 0V, T
amb
= +25°C (unless otherwise specified)
TS274C/AC
Parameter
Conditions
Min
V
o
= 1.4V, V
ic
= 0V
TS274C/I
TS274AC/AI
V
io
Input offset voltage
T
min
≤
T
amb
≤
T
max
TS274C/I
TS274AC/AI
2
V
ic
= 5V, V
o
= 5V
T
min
≤
T
amb
≤
T
max
V
ic
= 5V, V
o
= 5V
T
min
≤
T
amb
≤
T
max
V
id
= 100mV, R
L
= 10kΩ
T
min
≤
T
amb
≤
T
max
V
id
= -100mV
V
iC
= 5V, R
L
= 10kΩ,
V
o
= 1V to 6V
T
min
≤
T
amb
≤
T
max
A
v
= 40dB, R
L
= 10kΩ,
C
L
= 100pF, f
in
= 100kHz
V
ic
= 1V to 7.4V, V
o
= 1.4V
V
CC+
= 5V to 10V, V
o
= 1.4V
A
v
= 1, no load, V
o
= 5V
T
min
≤
T
amb
≤
T
max
65
60
10
7
3.5
80
70
1000 1500
1600
60
45
5.5
40
30
f = 1kHz, R
s
= 100Ω
30
120
65
60
15
8.2
8.1
1
100
1
150
8.4
50
10
6
3.5
80
70
1000 1500
1700
60
45
5.5
40
30
30
120
MHz
dB
dB
µA
mA
mA
V/µs
Degrees
%
nV/
√
Hz
dB
15
V/mV
8.2
8
8.4
50
1
300
Typ
Max Min Typ
Max
TS274I/AI
Unit
1.1
0.9
10
5
12
6.5
1.1
0.9
10
5
12
6.5
mV
mV
µV/°C
DV
io
I
io
I
ib
V
OH
V
OL
A
vd
Input offset voltage drift
Input offset current
(1)
Input bias current
(1)
High level output voltage
Low level output voltage
Large signal voltage gain
2
1
200
pA
pA
V
mV
GBP
CMR
SVR
I
CC
I
o
I
sink
SR
φm
K
OV
e
n
Gain bandwidth product
Common mode rejection
ratio
Supply voltage rejection
ratio
Supply current (per
amplifier)
Output short circuit current V
o
= 0V, V
id
= 100mV
Output sink current
Slew rate at unity gain
Phase margin at unity gain
Overshoot factor
Equivalent input noise
voltage
V
o
= V
CC
, V
id
= -100mV
,
R
L
= 10kΩ C
L
= 100pF,
V
in
= 3 to 7V
A
v
= 40dB, R
L
= 10kΩ
,
C
L
= 100pF
V
o1
/V
o2
Channel separation
1. Maximum values including unavoidable inaccuracies of the industrial test.
5/14
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