March 1997
NDS8410A
Single N-Channel Enhancement Mode Field Effect Transistor
General Description
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
10.8 A, 30 V. R
DS(ON)
= 0.012
Ω
@ V
GS
= 10 V
R
DS(ON)
= 0.017
Ω
@ V
GS
= 4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
NDS8410A
30
±20
10.8
50
2.5
1.2
1
-55 to 150
Units
V
V
A
W
T
J
,T
STG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS8410A Rev.C1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125°C
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 10.8 A
T
J
= 125°C
V
GS
= 4.5 V, I
D
= 9 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= 10 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 10.8 A
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
50
25
1
0.8
1.45
1
0.0105
0.015
0.015
30
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
3
2.1
0.012
0.022
0.017
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
1430
790
210
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 15 V,
I
D
= 10.8 A, V
GS
= 10 V
V
DD
= 10 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
Ω
12
18
65
37
45
5.5
10.5
20
30
100
80
60
ns
ns
ns
ns
nC
nC
nC
NDS8410A Rev.C1
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
2.1
(Note 2)
Units
A
V
ns
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
S
= 10.8 A
1.2
80
V
GS
= 0V, I
F
= 2.1 A, dI
F
/dt = 100 A/µs
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
T
J
−
T
A
R
θ
JC
+
R
θ
CA
(
t
)
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 50
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 105
o
C/W when mounted on a 0.04 in
2
pad of 2oz copper.
c. 125
o
C/W when mounted on a 0.006 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDS8410A Rev.C1
Typical Electrical Characteristics
50
I
D
, DRAIN-SOURCE CURRENT (A)
40
4.0
3.5
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 10V
6.0
4.5
2.5
2
V
GS
= 3.5 V
4.0
30
1.5
20
3.0
4.5
5.0
6.0
7.0
10
2.5
1
10
0
0
0.5
1
1.5
2
2.5
3
0.5
0
10
20
30
I
D
, DRAIN CURRENT (A)
40
50
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.6
1.8
I
D
= 10.8A
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 10V
1.6
1.4
1.2
1
0.8
0.6
0.4
DRAIN-SOURCE ON-RESISTANCE
1.4
V
GS
= 10V
TJ = 125°C
R
DS(ON)
, NORMALIZED
1.2
25°C
1
-55°C
0.8
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0
10
20
30
I
D
, DRAIN CURRENT (A)
40
50
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
60
1.3
V
DS
= 10V
50
T J = -55°C
125
25
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= V
GS
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
I
D
= 250µA
I
D
, DRAIN CURRENT (A)
40
30
20
10
0
1
1.5
2
2.5
3
3.5
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
4.5
5
V
GS(th)
, NORMALIZED
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
Figure 5. Transfer Charateristics
.
Figure 6. Gate Threshold Variation
with Temperature
.
NDS8410A Rev.C1
Typical Electrical Characteristics
(continued)
1.12
40
20
10
DRAIN-SOURCE BREAKDOWN VOLTAGE
V
GS
= 0V
TJ = 125°C
I
D
= 250µA
1.08
I
S
, REVERSE DRAIN CURRENT (A)
BV
DSS
, NORMALIZED
1
1.04
25°C
0.1
-55°C
0.01
1
0.96
0.001
0.92
-50
0.0001
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
0.3
0.6
0.9
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage
Variation with Temperature
.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
4000
3000
, GATE-SOURCE VOLTAGE (V)
2000
10
I
8
D
= 10.8A
V
DS
= 5V
10V
15V
Ciss
CAPACITANCE (pF)
1000
Coss
6
500
300
4
f = 1 MHz
V
GS
= 0 V
100
0 .1
Crss
V
0
20
30
0
0 .2
0 .5
1
2
5
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
2
10
Q
g
20
30
, GATE CHARGE (nC)
40
50
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
t
d(on)
t
on
t
r
90%
t
off
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
DUT
V
GS
V
OUT
R
GEN
10%
10%
INVERTED
G
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS8410A Rev.C1
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