D a t a S h e et , V 3 . 2 , J u l y 2 00 1
C167CR
C167SR
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
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The information herein is given to describe certain components and shall not be considered as warranted
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circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
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D a t a S h e et , V 3 . 2 , J u l y 2 00 1
C167CR
C167SR
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C167CR
Revision History:
Previous Version:
2001-07
2000-04
2000-02
1999-10
1999-06
1999-03
1998-03
07.97 / 12.96
12.96
06.95
06.94 / 05.93
V3.1
V3.0
(Introduction of clock-related timing)
(Summarizes and replaces all older docs)
(C167SR/CR, 25 MHz Addendum)
(C167CR-4RM)
(C167CR-16RM)
(C167CR, C167SR)
(C167)
V3.2
Page
Several
4
5
10
46
58
69
1)
Subjects (major changes since last revision)
Minor typos corrected
Pin designations corrected (pins 108, 99, 98)
Port 8 designations corrected
Direction for P1H.4
…
P1H.7 corrected
Note 4 added, notes 8, 9 updated
Note 2 detailed
Package drawing updated
1)
New package due to new assembly line. P-MQFP-144-1 for current deliveries only, will be discontinued.
Controller Area Network (CAN): License of Robert Bosch GmbH
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16-Bit Single-Chip Microcontroller
C166 Family
C167CR/C167SR
C167CR/C167SR
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
– 400/303 ns Multiplication (16
×
16 bit), 800/606 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
– 2 KBytes On-Chip Extension RAM (XRAM)
– 128/32 KBytes On-Chip Mask ROM
• On-Chip Peripheral Modules
– 16-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8
µ
s
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects
(Full CAN / Basic CAN)
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet
1
V3.2, 2001-07
微控制器 MCU
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