Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
Non-volatile Program and Data Memories
– 8K / 16K Bytes of In-System Self-Programmable Flash
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB boot-loader programmed by default in the factory
• In-System Programming by on-chip Boot Program hardware-activated after
reset
• True Read-While-Write Operation
– 512 Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification REV 2.0
– 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s
– Fully independant 176 bytes USB DPRAM for endpoint memory allocation
– Endpoint 0 for Control Transfers: from 8 up to 64-bytes
– 4 Programmable Endpoints:
• IN or Out Directions
• Bulk, Interrupt and IsochronousTransfers
• Programmable maximum packet size from 8 to 64 bytes
• Programmable single or double buffer
– Suspend/Resume Interrupts
– Microcontroller reset on USB Bus Reset without detach
– USB Bus Disconnection on Microcontroller Request
– USB pad multiplexed with PS/2 peripheral for single cable capability
Peripheral Features
– PS/2 compliant pad
– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit
PWM channels)
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode
(three 8-bit PWM channels)
– USART with SPI master only mode and hardware flow control (RTS/CTS)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
On Chip Debug Interface (debugWIRE)
Special Microcontroller Features
– Power-On Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
•
•
8-bit
Microcontroller
with
8/16K Bytes of
ISP Flash
and USB
Controller
AT90USB82
AT90USB162
•
•
•
7707D–AVR–07/08
•
•
•
•
– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
– 22 Programable I/O Lines
– QFN32 (5x5mm) / TQFP32 packages
Operating Voltages
– 2.7 - 5.5V
Operating temperature
– Industrial (-40°C to +85°C)
Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
2
AT90USB82/162
7707D–AVR–07/08
AT90USB82/162
1. Pin Configurations
Figure 1-1.
Pinout AT90USB82/162
32 31 30 29 28 27 26 25
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
PC5 ( PCINT9/ OC.1B)
UCAP
PC4 (PCINT10)
AVCC
UVCC
D- / SDATA
D+ / SCK
UGND
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
AVCC
UVCC
D- / SDATA
D+ / SCK
UCAP
PC4 (PCINT10)
9 10 11 12 13 14 15 16
(RTS / INT6) PD6
(CTS / HWB / T0 / INT7) PD7
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
(INT5) PD4
(XCK / PCINT12) PD5
(SS / PCINT0) PB0
(TXD1 / INT3) PD3
32 31 30 29 28 27 26 25
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
PC5 ( PCINT9/ OC.1B)
1
2
3
4
5
6
7
8
QFN32
24
23
22
21
20
19
18
17
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
UGND
1
2
3
4
5
6
7
8
(TXD1 / INT3) PD3
VQFP32
24
23
22
21
20
19
18
17
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
9 10 11 12 13 14 15 16
(INT5) PD4
(XCK / PCINT12) PD5
(RTS / INT6) PD6
(CTS / HWB / T0 / INT7) PD7
(SS / PCINT0) PB0
Note:
The large center pad underneath the QFN packages is made of metal and must be connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
3
7707D–AVR–07/08
2. Overview
The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By exe-
cuting powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Block Diagram
Figure 2-1.
PD7 - PD0
PC7 - PC0
PB7 - PB0
PORTD DRIVERS
PORTC DRIVERS
PORTB DRIVERS
ANALOG
COMPARATOR
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
8-BIT DA TA BUS
VCC
POR - BOD
RESET
GND
INTERNAL
OSCILLATOR
CALIB. OSC
Debug-Wire
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
OSCILLATOR
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
TIMING AND
CONTROL
PROGRAMMING
LOGIC
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
UVcc
INTERRUPT
UNIT
ON-CHIP
3.3V
REGULATOR
1uF
INSTRUCTION
DECODER
RESET
XTAL1
XTAL2
4
AT90USB82/162
7707D–AVR–07/08
+
-
UCap
CONTROL
LINES
ALU
EEPROM
PLL
STATUS
REGISTER
USB
D+/SCK
D-/SDATA
USART1
SPI
PS/2
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
AT90USB82/162
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The AT90USB82/162 provides the following features: 8K / 16K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 22 general
purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with com-
pare modes and PWM, one USART, a programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system
and programming and five software selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue func-
tioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crys-
tal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption. In Extended Standby mode, the main Oscillator
continues to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The AT90USB82/162 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-
tors, and evaluation kits.
2.2
2.2.1
Pin Descriptions
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90USB82/162 as listed on
page 74.
5
7707D–AVR–07/08
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