Microcomputer Components
SAB 80C517A/83C517A-5
8-Bit CMOS Single-Chip Microcontroller
Addendum to User's Manual SAB 80C517/80C537 05.94
Edition 05.94
This edition was realized using the software
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SAB 80C517A/83C517A-5
Revision History:
05.94
Previous Version:
Page
3-8
4-1
5-3
5-10/5-11
11.92
Subjects (major changes since last revision 11.92)
S0RELL adresses corrected
HWPD pin number corrected
T
S
/
T
C
in table 5-1 corrected
CC4EN bit names and table 5-3 corrected
Device Specifications SAB 80C517A/83C517A-5
Revision History:
05.94
Previous Releases:
Page
5
4
6-14
several
2
25,26,30
33
39
57
60
62
65
several
66
68
Page
25
51
65
67
74
Page
47
01.94/08.93/11.92/10.91/04.91
Subjects (changes since last revision 04.91)
Pin configuration P-MQFP-100-2 added
Pin differences updated
Pin numbers for P-MQFP-100-2 package added
Correction of P-MRFP-100 into P-MQFP-100-2
Ordering information for – 40 to + 110
°C
versions
Correction of register names S0RELL, SCON, ADCON, ICRON and SBUF
Figure 4 corrected
Figure 8 corrected
PE/SWD function description completed
Correct ordering numbers
Test condition for
V
OH
,
V
OH1
corrected
t
PXIZ
name corrected
t
AVIV
,
t
AZPL
values corrected
Minimum clock frequence is now 3.5 MHz
t
QVWH
(data setup before WR) corrected and added
t
LLAX2
corrected
Subjects (changes since last version 08.93)
Corrected SFR name S0RELL
Below “Termination of HWPD Mode”: 4th paragraph with ident corrected
Description of
t
LLIV
corrected
Program Memory Read Cycle:
f
PXAV
added
Oscillator circuit drawings: MQFP-100-2 pin numbers added.
Subjects (changes since last revision 01.94)
Minor changes on several pages
Table 6 corrected
80C517A/83C517A-5
Contents
Page
1
2
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
4
4.1
4.2
4.3
5
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.5
6
6.1
6.2
6.3
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Program Memory, ROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Architecture for the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Accesses to XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Control of XRAM in the SAB 80C517A . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Additional Hardware Power Down Mode in the SAB 80C517A . . . . . . . . . . 4-1
Hardware Power Down Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Fast internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Digital I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
10-bit A/D-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Additional Compare Mode for the Concurrent Compare Unit . . . . . . . . . . . 5-8
New Baud Rate Generators for Serial Channel 0 and Serial Channel 1 . . 5-14
Serial Channel 0 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Serial Channel 1 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Modified Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Additional Interrupt for Compare Registers CM0 to CM7 . . . . . . . . . . . . . . . 6-1
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Semiconductor Group
Introduction
1
Introduction
The SAB 80C517A is a superset of the high end microcontroller SAB 80C517.
While maintaining all architectural and operational characteristics of the SAB 80C517 the
SAB 80C517A incorporates more on-chip RAM as well as some enhancements in the compare /
capture unit. The oscillator watchdog got an improved functionality. Also the operating frequency is
higher than that of the SAB 80C517.
SAB 80C517A / 83C517A-5
In this manual, any reference made to the SAB 80C517A applies to both versions, the
SAB 80C517A and the SAB 83C517A-5, unless otherwise noted. Furthermore only new features of
the SAB 80C517A in addition to the features of the SAB 80C517A/83C517A-5 are described. For
additional reference, the user’s manual of the SAB 80C517/80C537 (Ord. No. B258-H6075-G1-X-
7600) should be used.
Semiconductor Group
1-1
FPGA/CPLD
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