Crystal-to-LVPECL Clock Synthesizer
ICS843312
DATA SHEET
General Description
The ICS843312 is a high frequency clock generator. The ICS843312
uses an external 25MHz crystal to synthesize 312.5MHz and
125MHz clocks. The ICS843312 has excellent RMS period jitter
performance.
The ICS843312 operates at full 3.3V and 2.5V, or mixed 3.3V/2.5V
supply modes and is available in a fully RoHS compliant 32-lead
VFQFN package.
Features
•
•
•
•
•
•
•
•
Ten differential LVPECL outputs for 312.5MHz and 125MHz
Crystal oscillator interface designed for 18pF, 25MHz parallel
resonant crystal
RMS phase jitter at 125MHz (1.875MHz - 20MHz):
0.45ps (typical)
RMS phase jitter at 312.5MHz (1.875MHz - 20MHz):
0.31ps (typical)
Output duty cycle: 45% – 55%, at 125MHz
Full 3.3V and 2.5V, or mixed 3.3V/2.5V supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Output Frequency Table
Crystal Frequency (MHz)
25
25
Feedback Divider
25
25
VCO Frequency (MHz)
625
625
Output Divider
÷2
÷5
Output Frequency (MHz)
312.5
125
Block Diagram
BYPASS
Pulldown
TEST_CLK
Pulldown
25MHz
1
6
QA[0:5]
nQA[0:5]
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
625MHz
÷5
0
M = ÷25
2
QB[0:1]
nQB[0:1]
÷2, ÷5
SELB
Pulldown
Pin Assignment
TEST_CLK
BYPASS
SELB
nQA0
V
CCA
V
CCO
QA0
V
CC
÷2
2
QC[0:1]
nQC[0:1]
32 31 30 29 28 27 26 25
XTAL_IN
XTAL_OUT
V
CC
nQC1
QC1
nQC0
QC0
V
CCO
1
2
3
4
5
6
7
8
9
nQB0
24
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
ICS843312
32 VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
10 11 12 13 14 15 16
nQA5
nQB1
V
CCO
QB0
QB1
QA5
V
EE
23
22
21
20
19
18
17
ICS843312AK REVISION B SEPTEMBER 28, 2010
1
©2010 Integrated Device Technology, Inc.
ICS843312 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
2
3, 32
4, 5
6, 7
8, 16, 25
9, 10
11, 12
13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28
29
30
31
Name
XTAL_IN
XTAL_OUT
V
CC
nQC1/QC1
nQC0/QC0
V
CCO
nQB0/QB0
nQB1/QB1
V
EE
nQA5/QA5
nQA4/QA4
nQA3/QA3
nQA2/QA2
nQA1/QA1
nQA0/QA0
V
CCA
BYPASS
SELB
TEST_CLK
Input
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Core supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
A HIGH on BYPASS signal allows TEST_CLK to propagate to output dividers and
bypass the PLL. a LOW on BYPASS signal allows VCO frequency to propagate to
the output dividers. See Table 3B. LVCMOS/LVTTL interface levels.
Selects the output divider value. See Table 3A. LVCMOS/LVTTL interface levels.
Single-ended input test clock. LVCMOS/LVTTL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
Function Tables
Table 3A. SELB Function Table
Input
SELB
0
1
Bank B Output Divider
÷5
÷2
Table 3B. Bypass Function Table
Input
BYPASS
0
1
Device Configuration
PLL Mode
Bypass the PLL
ICS843312AK REVISION B SEPTEMBER 28, 2010
2
©2010 Integrated Device Technology, Inc.
ICS843312 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.33
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
179
33
Units
V
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
CC
– 0.23
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
CC
2.625
168
23
Units
V
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.33
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
164
33
Units
V
V
V
mA
mA
ICS843312AK REVISION B SEPTEMBER 28, 2010
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©2010 Integrated Device Technology, Inc.
ICS843312 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Table 4D. LVCMOS/LVTTL DC Characteristics,
T
A
=
0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input
High Current
Input
Low Current
TEST_CLK,
BYPASS, SELB
TEST_CLK,
BYPASS, SELB
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4E. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
Output Low Voltage
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
Table 4F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
CCO
= 2.5V ± 5%,V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
Output Low Voltage
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.5
1.0
Units
V
V
V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
Ω
pF
ICS843312AK REVISION B SEPTEMBER 28, 2010
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©2010 Integrated Device Technology, Inc.
ICS843312 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
Output divider = ÷2
Output divider = ÷5
312.5MHz,
Integration Range: 1.875MHz - 20MHz
125MHz,
Integration Range: 1.875MHz - 20MHz
20% to 80%
f
OUT
= 125MHz
f
OUT
= 312.5MHz
200
45
40
Minimum
Typical
312.5
125
0.31
0.45
700
55
60
100
Maximum
Units
MHz
MHz
ps
ps
ps
%
%
ms
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
t
R
/ t
F
odc
t
LOCK
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to phase noise plots.
Table 6B. AC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
Output divider = ÷2
Output divider = ÷5
312.5MHz,
Integration Range: 1.875MHz - 20MHz
125MHz,
Integration Range: 1.875MHz - 20MHz
20% to 80%
f
OUT
= 125MHz
f
OUT
= 312.5MHz
200
45
40
Minimum
Typical
312.5
125
0.45
0.55
700
55
60
100
Maximum
Units
MHz
MHz
ps
ps
ps
%
%
ms
tjit(Ø)
RMS Phase Jitter, (Random)
t
R
/ t
F
odc
t
LOCK
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
Table 6C. AC Characteristics,
V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
=
0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
Output divider = ÷2
Output divider = ÷5
312.5MHz,
Integration Range: 1.875MHz - 20MHz
125MHz,
Integration Range: 1.875MHz - 20MHz
20% to 80%
f
OUT
= 125MHz
f
OUT
= 312.5MHz
200
45
40
Minimum
Typical
312.5
125
0.31
0.45
700
55
60
100
Maximum
Units
MHz
MHz
ps
ps
ps
%
%
ms
tjit(Ø)
RMS Phase Jitter, (Random)
t
R
/ t
F
odc
t
LOCK
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
ICS843312AK REVISION B SEPTEMBER 28, 2010
5
©2010 Integrated Device Technology, Inc.
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