Low Skew, 1-To-4,
Crystal Oscillator/LVCMOS-To-3.3V LVPECL
Fanout Buffer
General Description
The ICS8535I-31 is a low skew, high performance
1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
HiPerClockS™
LVPECL fanout buffer. The ICS8535I-31 has
selectable single ended clock or crystal inputs. The
single ended clock input accepts LVCMOS or LVTTL
input levels and translate them to 3.3V LVPECL levels. The output
enable is internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the clock
enable pin.
ICS8535I-31
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four differential 3.3V LVPECL outputs
Selectable LVCMOS/LVTTL CLK or crystal inputs
CLK can accept the following input levels: LVCMOS, LVTTL
Maximum output frequency: 266MHz
Output skew: 30ps (typical)
Part-to-part skew: 200ps (maximum)
Propagation delay: 1.75ns (maximum)
Additive phase jitter, RMS: 0.057ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Replaces the ICS8535I-11
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Guaranteed output and part-to-part skew characteristics make the
ICS8535I-31 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
CLK_EN
Pullup
D
Q
LE
0
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
V
EE
CLK_EN
CLK_SEL
CLK
nc
XTAL_IN
XTAL_OUT
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
CLK
XTAL_IN
Pulldown
OSC
XTAL_OUT
1
CLK_SEL
Pulldown
ICS8535I-31
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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©2010 Integrated Device Technology, Inc.
ICS8535I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
Name
V
EE
CLK_EN
Power
Input
Pullup
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects XTAL inputs
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Positive supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3
4
5, 8, 9
6,
7
10, 13, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
CLK
nc
XTAL_IN,
XTAL_OUT
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Unused
Input
Power
Output
Output
Output
Output
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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©2010 Integrated Device Technology, Inc.
ICS8535I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Q0:Q3
Disabled; Low
Disabled; Low
Enabled
Enabled
Outputs
nQ0:nQ3
Disabled; High
Disabled; High
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown
in
Figure 1.
In the active mode, the state of the outputs are a function of the CLK input as described in
Table 3B.
Disabled
Enabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK
0
1
Q0:Q3
LOW
HIGH
Outputs
nQ0:nQ3
HIGH
LOW
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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©2010 Integrated Device Technology, Inc.
ICS8535I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
65
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK, CLK_SEL
Input High Current
CLK_EN
CLK, CLK_SEL
I
IL
Input Low Current
CLK_EN
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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©2010 Integrated Device Technology, Inc.
ICS8535I-31
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
– 2V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
12
Test Conditions
Minimum
Typical
Fundamental
40
50
7
1
MHz
Maximum
Units
Ω
pF
mW
AC Electrical Characteristics
Table 6. AC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
46
155.52MHz, Integration Range:
12kHz – 20MHz
1.4
0.057
30
200
600
54
Test Conditions
Minimum
Typical
Maximum
266
1.75
Units
MHz
ns
ps
ps
ps
ps
%
All parameters measured at ƒ
≤
266MHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from V
CC
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crossing point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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©2010 Integrated Device Technology, Inc.
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