700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-
D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
ICS8442B
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS8442B is a general purpose, dual output Crystal-to-
Differential LVDS High Frequency Synthesizer . The ICS8442B
has a selectable TEST_CLK or crystal input. The TEST_CLK
input accepts LVCMOS or LVTTL input levels and translates
them to LVDS levels. The VCO operates at a frequency range
of 250MHz to 700MHz.The VCO frequency is programmed in
steps equal to the value of the input reference or crystal fre-
quency. The VCO and output frequency can be programmed
using the serial or parallel interface to the configuration logic.
The low phase noise characteristics of the ICS8442B makes
it an ideal clock source for Gigabit Ethernet and Sonet appli-
cations.
F
EATURES
•
Dual differential LVDS outputs
•
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
•
Output frequency range: 31.25MHz to 700MHz
•
Crystal input frequency range: 10MHz to 25MHz
•
VCO range: 250MHz to 700MHz
•
Parallel or serial interface for programming counter
and output dividers
•
RMS period jitter: 2.7ps (typical)
•
Cycle-to-cycle jitter: 18ps (typical)
•
3.3V supply voltage
•
0°C to 85°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
VCO_SEL
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
M4
M3
M2
M1
M0
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
0
1
M5
M6
M7
M8
N0
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8442
21
20
19
18
17
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
1
÷
1
÷
2
÷
4
÷
8
FOUT0
nFOUT0
FOUT1
nFOUT1
N1
nc
GND
9 10 11 12 13 14 15 16
TEST
V
DD
FOUT1
nFOUT1
V
DD
FOUT0
nFOUT0
GND
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
ICS 8442B
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8442BY REVISION A NOVEMBER 18, 2013
1
700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8442B features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is fed into
the phase detector. A 25MHz crystal provides a 25MHz
phase detector reference frequency. The VCO of the PLL
operates over a range of 250MHz to 700MHz. The output of
the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVDS output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8442B support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In paral-
lel mode, the nP_LOAD input is initially LOW. The data on
inputs M0 through M8 and N0 and N1 is passed directly to
the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and
the M divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a result, the
M and N bits can be hardwired to set the M divider and N
output divider to a specific default state that will automati-
cally occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relationship be-
tween the VCO frequency, the crystal frequency and the M
divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
≤
M
≤
28. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1 T0
TEST Output
0
0
1
1
0
1
0
1
LOW
S_Data, Shift Register Input
Output of M divider
CMOS FOUT
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
ICS8442BY REVISION A NOVEMBER 18, 2013
2
700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8 , 16
9
10, 13
11, 12
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
GND
TEST
V
DD
FOUT1, nFOUT1
FOUT0, nFOUT0
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Type
Pullup
M divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. LVDS interface levels.
Differential output for the synthesizer. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not effect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal oscillator or test inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects TEST_CLK when
LOW. LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
Description
17
MR
Input
Pulldown
18
19
20
21
22
23
24, 25
26
27
S_CLOCK
S_DATA
S_LOAD
V
DDA
XTAL_SEL
TEST_CLK
XTAL_IN,
XTAL_OUT
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8442BY REVISION A NOVEMBER 18, 2013
3
700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. When HIGH, forces the outputs to a differential
LOW state (FOUTx = LOW and nFOUTx = HIGH), but
does not effect loaded M, N, and T values.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
275
•
•
650
675
M Divide
10
11
•
•
26
27
256
M8
0
0
•
•
0
0
128
M7
0
0
•
•
0
0
64
M6
0
0
•
•
0
0
32
M5
0
0
•
•
0
0
16
M4
0
0
•
•
1
1
8
M3
1
1
•
•
1
1
4
M2
0
0
•
•
0
0
2
M1
1
1
•
•
1
1
1
M0
0
1
•
•
0
1
0
700
28
0
0
0
0
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
250
125
62.5
31.25
Maximum
700
350
175
87.5
ICS8442BY REVISION A NOVEMBER 18, 2013
4
700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
182
16
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol Parameter
V
IH
Input
High Voltage
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
TEST_CLK
M0-M8, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD,
XTAL_SEL, VCO_SEL
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
S_LOAD,
M5, XTAL_SEL, VCO_SEL
V
OH
Test Conditions
Minimum Typical
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
-5
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
µA
Units
V
V
V
V
µA
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Input
Low Current
-150
V
0.5
V
Output
TEST; NOTE 1
2.6
High Voltage
Output
TEST; NOTE 1
V
OL
Low Voltage
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.4
Test Conditions
Minimum
250
Typical
450
Maximum
600
50
1.6
50
Units
mV
mV
V
mV
ICS8442BY REVISION A NOVEMBER 18, 2013
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
