1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
1.3-MEGAPIXEL CMOS
ACTIVE-PIXEL DIGITAL
IMAGE SENSOR
Description
The MI-MV13 is a 1,280H x 1,024V (1.3 megapixel)
CMOS digital image sensor capable of 500 frames-per-
second (fps) operation. Its TrueSNAP™ electronic
shutter allows simultaneous exposure of the entire
pixel array. Available in color or monochrome, the sen-
sor has on-chip 10-bit analog-to-digital converters
(ADCs), which are self-calibrating, and a fully digital
interface. The chip's input clock rate is 66 MHz at
approximately 500 fps, providing compatibility with
many off-the-shelf interface components.
The sensor has ten 10-bit-wide digital output ports.
Its open architecture design provides access to internal
operations. ADC timing and pixel-read control are
integrated on-chip. At 60 fps, the sensor dissipates less
than 150mW, and at 500 fps less than 500mW; it oper-
ates on a 3.3V supply. Pixel size is 12 microns square,
and digital responsivity is 1,600 bits per lux-second.
MT9M413
Micron Part Number: MT9M413C36STC
Features/Top Level Specifications
• Array Format: 1,280H x 1,024 V (1,310,720 pixels)
• Pixel Size and Type: 12.0µm x 12.0µm TrueSNAP
(shuttered-node active pixel)
• Sensor Imaging Area: H: 15.36mm, V: 12.29mm,
Diagonal: 19.67mm
• Frame Rate: 0–500+ fps @ (1,280 x 1,024), >10,000
fps with partial scan, [e.g. 0–4000 fps @ (1,280 x 128)]
• Output Data Rate: 660 Mbs (master clock 66 MHz,
~500 fps)
• Power Consumption: < 500 mW @ 500 fps; <150 mW
@ 60 fps
• Digital Responsivity: Monochrome: 1,600 bits per
lux-second @ 550nm; ADC reference @ 1V
• Internal Intra-Scene Dynamic Range: 59dB
• Supply Voltage: +3.3V
• Operating Temperature: -5°C to +60°C
• Output: 10-bit digital through 10 parallel ports
• Conversion Gain = 13µV/e
-
•
•
•
•
•
•
•
Color: Monochrome or color RGB
Shutter: TrueSNAP freeze-frame electronic shutter
Shutter Efficiency: >99.9%
Shutter Exposure Time: 2µs to > 33 msec
ADC: On-chip, 10-bit column-parallel
Package: 280-pin ceramic PGA
Programmable Controls: Open architecture
On-chip:
•ADC controls
•Output multiplexing
•ADC calibration
Off-chip:
•Window size and location
•Frame rate and data rate
•Shutter exposure time (integration time)
•ADC reference
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©2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
General
The MI-MV13 is a 1280H x 1024V (1.31 megapixel)
CMOS digital image sensor capable of 500 frames-per-
second (fps) operation. Its TrueSNAP™ electronic
shutter allows simultaneous exposure of the entire
pixel array. Available in color or monochrome, the sen-
sor has on-chip 10-bit analog-to-digital converters
(ADCs), which are self-calibrating, and a fully digital
interface. The chip’s input clock rate is 66 MHz at
approximately 500 fps, providing compatibility with
many off-the-shelf interface components as shown in
Figure 1.
The sensor has ten (10) 10-bit-wide digital output
ports. Its open architecture design provides access to
internal operations. ADC timing and pixel-read control
are integrated on-chip. At 60 fps, the sensor dissipates
less than 150 mW, and at 500 fps less than 500 mW; it
operates on a 3.3V supply. Pixel size is 12 microns
square and digital responsivity is 1600 bits per lux-sec-
ond.
The MI-MV13 CMOS image sensor has an open
architecture to provide access to its internal opera-
tions. A complete camera system can be built by using
the chip in conjunction with the following external
devices:
• An FPGA/CPLD/ASIC controller, to manage the
timing signals needed for sensor operation.
• A 20mm diagonal lens.
• Biasing circuits and bypass capacitors.
Figure 1: A Camera System Using the MI-MV13 CMOS Image Sensor
+3.3V
ADC Bias
Off-Chip
Port 1
Port 2
D0~D9
D10~D19
D20~D29
D30~D39
D40~D49
D50~D59
D60~D69
D70~D79
D80~D89
D90~D99
On-Chip Control
Controller
(FPGA, CPLD, ASIC, etc.)
Control
Timing
Pixel Array
(1280H x 1024V)
Memory
System
Clock
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
ADC
System
Clock
System
Interface
On-Chip
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Figure 2: Sensor Architecture (not to scale)
SENSE AMPS
MEMORY
TOP ADCs
DIGITAL
CONTROL
PIXEL ARRAY
BOTTOM ADCs
Figure 3: Signal Path Diagram
Pixel
TX_N
Per Column Processing
Pixel
Memory
Bias
VLN1
Bias
VLP
VREF2
ADC
Calibration
DAC
7
VREF1 VREF4
Photo
Detector
PG_N
VRST_PIX
Buffer
Sample
& Hold
∑
∑
ADC
BIAS
VLN2
10
To
ADC
registers
Offset
(VREF3-VCLAMP3)/20
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
Figure 4: Functional Block Diagram
TX_N
PG_N
PIXEL ARRAY
Row Decoder
Row Driver
ROW
10
LogicRST
Row
Timing
Block
S/H
RowSTRT
ADC
#1
ADC
#2
...
ADC
#1280
RowDone
Sample
1280 x 10 SRAM
ADC Register
1280 x 10 SRAM
Output Register
Column Decoder
Pads
10 x 10
Data Shift /
Read
SRAM
Read
Control
Shift
Sense Amps
Output Ports
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
External Control Sequence
The MI-MV13 includes on-chip timing and control
circuitry to control most of the pixel, ADC, and output
multiplexing operations. However, the sensor still
requires a controller (FPGA, CPLD, ASIC, etc.) to guide
it through the full sequence of its operation.
With the TrueSNAP freeze-frame electronic shutter
signal charges are integrated in all pixels in parallel.
The charges are then sampled into pixel analog memo-
ries (one memory per pixel) and subsequently, row by
row, are digitized and read out of the sensor. The inte-
gration of photosignal is controlled by two control sig-
nals: PG_N and TX_N. To clear pixels and start new
integration, PG_N is made low. To transfer the data
into pixel memory, TX_N is made low. The time differ-
ence between the two procedures is the exposure time.
It should be noted that neither the PG_N or TX_N
pulses clear the pixel analog memory. Pixel memory
can be cleared during the previous readout (i.e., the
readout process resets the pixel analog memory), or by
applying PG_N and TX_N together (i.e., clearing both
pixel and pixel memory at the same time).
With the TrueSNAP freeze-frame electronic shutter
the sensor can operate in either simultaneous or
sequential mode in which it generates continuous
video output. In simultaneous mode, as a series of
frames are being captured, the PG_N and TX_N signals
are exercised while the previous frame is being read
out of the sensor. In simultaneous mode typically the
end of integration occurs in the last row of the frame
(row #1023) or in the last row of the window of interest.
The position of the start integration is then calculated
from the desired integration time. In sequential mode
the PG_N and TX_N signals are exercised to control the
integration time, and then digitization and readout of
the frame takes place. Alternatively, the sensor can run
in single frame or snapshot mode in which one image
is captured.
The sensor has a column-parallel ADC architecture
that allows the array of 1,280 analog-to-digital convert-
ers on the chip to digitize simultaneously the analog
data from an entire pixel row. The following input sig-
nals are utilized to control the conversion and readout
process:
Table 1:
Conversion and Readout
Process
DESCRIPTION
Row Address
Row Start
Load shift register
Data read enable
INPUT BUS
WIDTH
10-bit
1-bit
1-bit
1-bit
SIGNAL NAME
ROW_ADDR
ROW_STRT_N
LD_SHFT_N
DATA_READ_EN_N
The 10-bit ROW_ADDR (row address) input bus
selects the pixel row to be read for each readout cycle.
The ROW_STRT_N signal starts the process of reading
the analog data from the pixel row, the analog-to-digi-
tal conversion, and the storage of the digital values in
the ADC registers. When these actions are completed,
the sensor sends a response back to the system con-
troller using the ROW_DONE_N. Row address must be
valid for the first half of the row processing time (the
period between ROW_START_N and ROW_DONE_N).
The MI-MV13 contains a pipeline style memory
array, which is used to store the data after digitization.
This memory also allows the data from the previous
row conversion cycle to be read while a new conver-
sion is taking place.
The digital readout is controlled by lowering the
LD_SHFT_N
signal,
followed
by
the
DATA_READ_EN_N signal. LD_SHFT_N transfers the
digitized data from the ADC register to the output reg-
ister. DATA_READ_EN_N is used to enable the data
output from the output register. A new pixel row read-
out and conversion cycle can be started two clock
cycles after DATA_READ_EN_N is pulled low. The out-
put register allows the reading of the digital data from
the previous row to be performed at the same time as a
new conversion (pipeline mode). This means that the
total row time will be only that between when: (a) the
ROW_STRT_N signal is applied and ROW_DONE_N is
returned; and (b) LD_SHFT_N and DATA_READ_EN_N
are applied plus two clock cycles. The pipelined opera-
tion means there will always be 1 row of latency at the
start of sensor operation. The alternative to pipelined
operation is burst data operation in which a new pixel
row conversion is not initiated until after the output
register is emptied (and LD_SHFT_N has been taken
high). The ratio of line active and blanking times can
be adjusted to easily match a variety of display and
collection formats. See “Timing Diagram For One
Row” on page 7.
09005aef806807ca
MT9M413C36STC.fm - Ver. 3.0 1/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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