FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
May 2008
FOD0721, FOD0720, FOD0710
High CMR, 25Mbit/sec Logic Gate Optocoupler
Features
■
20kV/µs minimum CMR
■
40ns max. propagation delay
■
Data Rate, Non-Return Zero Coding
Description
The FOD0721/0720/0710 family utilizes Fairchild’s
patented coplanar packaging technology, Optoplanar
®
,
and optimized IC design to guarantee minimum 20kV/µs
Common Mode Noise Rejection (CMR) rating.
These high-speed logic gate optocouplers consist of a
high-speed AlGaAs LED driven by a CMOS IC coupled
to a CMOS detector IC, comprising an integrated photo-
diode, a high-speed transimpedance amplifier and a
voltage comparator with an output driver. The CMOS
technology coupled to the high efficiency of the LED
achieves low power consumption as well as very high
speed (40ns propagation delay, 6ns pulse width
distortion).
These devices are available in a compact 8-pin small
outline package.
■
■
■
■
– 25Mbit/sec (FOD0721 and FOD0720)
– 12.5Mbit/sec (FOD0710)
Pulse Width Distortion
– 6ns (FOD0721)
– 8ns (FOD0720 and FOD0710)
+5V CMOS compatibility
Extended industrial temperate range
– -40 to 100°C temperature range
Safety and regulatory approvals
– UL1577, 3750 VACrms for 1 min. (File #E90700,
Volume 2)
– IEC60747-5-2 pending approval
Applications
■
Industrial fieldbus communications
– Profibus, DeviceNet, CAN, RS485
■
Programmable logic control
■
Isolated data acquisition system
Package Dimensions
0.164 (4.16)
0.144 (3.66)
SEATING PLANE
0.202 (5.13)
0.182 (4.63)
0.143 (3.63)
0.123 (3.13)
0.010 (0.25)
0.006 (0.16)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
Note:
All dimensions are in inches (millimeters)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
Functional Block Diagram
V
DD1
1
V
I
2
8 V
DD2
7 NC
6 V
O
5 GND2
*
3
GND1 4
*: Pin 3 must be left unconnected
Truth Table
LED
V
I
H
OFF
L
ON
V
O
H
L
Pin Definitions
Pin Number
1
2
3
4
5
6
7
8
GND1
GND2
V
O
NC
V
DD2
Pin Name
V
DD1
V
I
Input Supply Voltage
Input Data
Pin Function Description
LED Anode – must be left unconnected
Input Ground
Output Ground
Output Data
Not Connected
Output Supply Voltage
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
2
FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
Absolute Maximum Ratings
(T
A
= 25°C unless otherwise specified.)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
OPR
T
SOL
V
DD1
V
I
I
I
V
DD2
V
D
I
O
PD1
PD2
Parameter
Storage Temperature
Operating Temperature
Lead Solder Temperature
Reflow Temperature Profile (Refer to Relow Profile)
Input Supply Voltage
Input Voltage
Input DC Current
Output Supply Voltage
Output Voltage
Average Output Current
Input Power Dissipation
Output Power Dissipation
Value
-55 to +125
-40 to +100
260 for 10 sec
0 to 6.0
-0.5 to V
DD1
+ 0.5
-10 to +10
0 to 6.0
-0.5 to V
DD2
+ 0.5
10
90
70
Units
°C
°C
°C
V
V
mA
V
V
mA
mW
mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
OPR
V
DD1
, V
DD2
V
IH
V
IL
t
r
, t
f
Supply Voltages
Parameter
Ambient Operating Temperature
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Time
Min.
-40
4.5
2.0
0
Max.
+100
5.5
V
DD1
0.8
1.0
Unit
°C
V
V
V
ms
• A 0.1µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8
• Pin 3 must be left unconnected
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
3
FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
Electrical Characteristics
(T
A
= -40°C to 100°C and 4.5V
≤
V
DD
≤
5.5V, all typicals are at T
A
= 25°C, V
DD
= 5V)
Symbol
I
DD1L
I
DD1H
I
DD1
I
I
I
DD2L
I
DD2H
V
OH
V
OH
V
OL
V
OL
Logic Low Output Voltage
Parameter
Logic Low Input Supply Current
Logic High Input Supply Current
Input Supply Current
Input Current
Logic Low Output Supply Current
Logic High Output Supply Current
Logic High Output Voltage
Test Conditions
V
I
= 0V
V
I
= V
DD1
Min.
Typ.
6.5
0.8
Max.
10.0
3.0
13.0
+10
Unit
mA
mA
mA
µA
mA
mA
V
V
INPUT CHARACTERISTICS
-10
V
I
= 0V
V
I
= V
DD1
I
O
= -20µA, V
I
= V
IH
I
O
= -4mA, V
I
= V
IH
I
O
= 20µA, V
I
= V
IL
I
O
= 4mA, V
I
= V
IL
4.4
4.0
5.5
5.3
5.0
4.8
0
0.5
OUTPUT CHARACTERISTICS
9
9
0.1
1.0
V
V
Isolation Characteristics
(T
A
= -40°C to +100°C unless otherwise specified.)
Symbol
V
ISO
R
ISO
C
ISO
Characteristics
Input-Output Isolation Voltage
Isolation Resistance
Isolation Capacitance
Test Conditions
f = 60Hz, t = 1.0 min, I
I-O
≤
10µA
(1)(2)
V
I-O
= 500V
(1)
V
I-O
= 0 , f = 1.0MHz
(1)
Min.
3750
10
11
Typ.* Max.
Unit
Vac
RMS
Ω
0.2
pF
*All typicals at T
A
= 25°C
Notes:
1. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
2. 3,750 VAC RMS for 1 minute duration is equivalent to 4,500 VAC RMS for 1 second duration.
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
4
FOD0721, FOD0720, FOD0710 — High CMR, 25Mbit/sec Logic Gate Optocoupler
Switching Characteristics
(T
A
= -40°C to 100°C and 4.5V
≤
V
DD
≤
5.5V, all typicals are at T
A
= 25°C, V
DD
= 5V)
Symbol
t
PHL
t
PLH
PWD
Parameter
Propagation Delay Time to
Logic Low Output
Propagation Delay Time to
Logic High Output
FOD0710
FOD0720
FOD0721
Test Conditions
C
L
= 15pF
C
L
= 15pF
Min.
Typ.
21
23
Max.
40
40
Unit
ns
ns
Pulse Width Distortion, | t
PHL
– t
PLH
|
PW = 80ns, C
L
= 15pF
PW = 40ns, C
L
= 15pF
PW = 40ns, C
L
= 15pF
2
2
2
8
8
6
12.5
25
C
L
=
15pF
(3)
5
4.5
V
I
= V
DD1
, V
O
> 0.8 V
DD2
V
CM
= 1000V
(4)
V
I
= 0V, V
O
< 0.8,
V
CM
= 1000V
(4)
20
20
40
40
20
ns
ns
ns
Mb/s
Mb/s
ns
ns
ns
kV/µs
kV/µs
Data Rate
t
PSK
t
R
t
F
|CM
H
|
|CM
L
|
FOD0710
FOD0720, FOD0721
Propagation Delay Skew
Output Rise Time (10%–90%)
Output Fall Time (90%–10%)
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
Notes:
3. t
PSK
is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given
temperature within the recommended operating conditions.
4. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge
of the common mode impulse signal. Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable (negative dVcm/dt on the trailing edge of the common pulse
signal, Vcm, to assure that the output will remain low.
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
5
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