RT9173D
Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator
General Description
The RT9173D is a simple, cost-effective and high-speed
linear regulator designed to generate termination voltage
in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific
interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices
requirements. The regulator is capable of actively sinking
or sourcing continuous 2A or up to 3A transient peak
current while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated to
track 1/2V
DDQ
by two external voltage divider resistors or
the desired output voltage can be pro-grammed by externally
forcing the REFEN pin voltage.
The RT9173D also incorporates a high-speed differential
amplifier to provide ultra-fast response in line/load transient.
Other features include extremely low initial offset voltage,
excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection.
The RT9173D are available in the SOP-8 (Exposed Pad)
surface mount packages.
Features
Ideal for DDR-I, DDR-II and DDR-III V
TT
Applications
Sink and Source Current
2A Continuous Current
Peak 3A for DDRI and DDRII
Peak 2.5A for DDRIII
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in
SOP-8 (Exposed
Pad) Packages
V
IN
and V
CNTL
No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free
Applications
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
Ordering Information
RT9173D
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
VIN
GND
REFEN
VOUT
2
8
7
GND
3
6
9
4
5
NC
NC
VCNTL
NC
SOP-8 (Exposed Pad)
DS9173D-07 April 2011
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1
RT9173D
Typical Application Circuit
V
CNTL
= 3.3V
V
IN
= 2.5V/1.8V/1.5V
R
1
VIN
VCNTL
C
IN
C
CNTL
R
TT
2N7002
EN
R
2
C
SS
RT9173D
REFEN
VOUT
GND
C
OUT
GND
R
1
= R
2
= 100kΩ, R
TT
= 50Ω / 33Ω / 25Ω
C
OUT(MIN)
= 10μF (Ceramic) + 1000μF under the worst case testing condition
C
SS
= 1μF, C
IN
= 470μF (Low ESR), C
CNTL
= 47μF
Test Circuit
2.5V/1.8V/1.5V
3.3V
VIN
1.25V/0.9V/0.75V
VCNTL
V
OUT
RT9173D
REFEN
VOUT
GND
Figure 1. Test Circuit for Typical Operating Characteristics Curves
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2
DS9173D-07 April 2011
RT9173D
Functional Pin Description
VIN (Pin 1)
Input voltage which supplies current to the output pin.
Connect this pin to a well-decoupled supply voltage. To
prevent the input rail from dropping during large load
transient, a large, low ESR capacitor is recommended to
use. The capacitor should be placed as close as possible
to the VIN pin.
GND [Pin 2, Exposed pad (9)]
Common Ground (Exposed pad is connected to GND).
The GND pad area should be as large as possible and
using many vias to conduct the heat into the buried GND
plate of PCB layer.
REFEN (Pin 3)
Reference voltage input and active low shutdown control
pin. Two resistors dividing down the VIN voltage on the pin
to create the regulated output voltage. Pulling the pin to
ground turns off the device by an open-drain, such as
2N7002, signal N-MOSFET.
VOUT (Pin 4)
Regulator output. VOUT is regulated to REFEN voltage
that is used to terminate the bus resistors. It is capable of
sinking and sourcing current while regulating the output
rail. To maintain adequate large signal transient response,
typical value of 1000
μ
F AL electrolytic capacitor with 10
μ
F
ceramic capacitors are recommended to reduce the effects
of current transients on VOUT.
VCNTL (Pin 6)
VCNTL supplies the internal control circuitry and provides
the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin
to 3.3V bias
supply to handle large output current with at least 10
μ
F
capacitor from this pin to GND.
NC (Pin 5, 7, 8)
No Internal Connect.
Function Block Diagram
VCNTL
VIN
Current Limit
Thermal Protection
REFEN
DS9173D-07 April 2011
+
-
EA
VOUT
GND
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3
RT9173D
Absolute Maximum Ratings
(Note 1)
6V
6V
1.33W
75°C/W
28°C/W
Input Voltage, V
IN
----------------------------------------------------------------------------------------------------
Control Voltage, V
CNTL
----------------------------------------------------------------------------------------------
Power Dissipation, P
D
@ T
A
= 25°C
SOP-8 (Exposed Pad) ----------------------------------------------------------------------------------------------
Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad),
θ
JA
----------------------------------------------------------------------------------------
SOP-8 (Exposed Pad),
θ
JC
----------------------------------------------------------------------------------------
Junction Temperature -----------------------------------------------------------------------------------------------
125°C
Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------
260°C
Storage Temperature Range ---------------------------------------------------------------------------------------
–65°C
to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions
(Note 4)
Input Voltage, V
IN
---------------------------------------------------------------------------------------------------- 2.5V to 1.5V
±
5%
Control Voltage, V
CNTL
---------------------------------------------------------------------------------------------- 5V or 3.3V
±
5%
Ambient Temperature Range --------------------------------------------------------------------------------------
−
40°C to 85°C
Junction Temperature Range --------------------------------------------------------------------------------------
−40°C
to 125°C
Electrical Characteristics
(V
IN
= 2.5V/1.8V/1.5V, V
CNTL
= 3.3V, V
REFEN
= 1.25V/0.9V/0.75V, C
OUT
= 10
μ
F (Ceramic), T
A
= 25° C, unless otherwise specified)
Parameter
Input
V
CNTL
Operation Current
Standby Current (Note 5)
Output (DDR / DDR II / DDR III)
Output Offset Voltage (Note 6)
Load Regulation (Note 7)
Protection
Current limit
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
REFEN Shutdown
Shutdown Threshold
Symbol
I
CNTL
I
STBY
I
OUT
= 0A
Test Conditions
Min
--
--
Typ
1
50
Max
2.5
90
Unit
mA
μA
V
REFEN
<
0.2V (Shutdown),
R
LOAD
= 180Ω
I
OUT
= 0A
I
OUT
= +2A
I
OUT
=
−2A
V
IN
= 2.5V/1.8V/1.5V
3.3V
≤
V
CNTL
≤
5V
3.3V
≤
V
CNTL
≤
5V
Enable
Shutdown
V
OS
ΔV
LOAD
−20
−20
--
--
+20
+20
mV
mV
I
LIM
T
SD
ΔT
SD
V
IH
V
IL
--
125
--
0.6
--
3.4
170
35
--
--
--
--
--
--
0.2
A
°C
°C
V
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DS9173D-07 April 2011
RT9173D
Note 1.
Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2.
θ
JA
is measured in the natural convection at T
A
= 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of
θ
JC
is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 3.
Devices are ESD sensitive. Handling precaution recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Note 5.
Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (V
IL
< 0.2V). It is measured with V
IN
= V
CNTL
= 5V.
Note 6.
V
OS
offset is the voltage measurement defined as V
OUT
subtracted from V
REFEN
.
Note 7.
Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
DS9173D-07 April 2011
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