Preliminary
GS881E18/36T-11/11.5/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
1.10 9/2000Features
• FT pin for user-configurable flow through or pipelined
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 100-lead TQFP package
-11
-11.5
-100
-80
-66
10 ns
10 ns 12.5 ns 15 ns
Pipeline tCycle 10 ns
4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns
3-1-1-1
t
KQ
I
DD
225 mA 225 mA 225 mA 200 mA 185 mA
11 ns 11.5 ns 12 ns
14 ns
18 ns
Flow
t
KQ
Through tCycle 15 ns
15 ns
15 ns
15 ns
20 ns
2-1-1-1
I
DD
180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 36 ByteSafe™
100 MHz–66 MHz
3.3 V V
DD
8Mb Sync Burst SRAMs
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18//36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
ByteSafe™ Parity Functions
Functional Description
Applications
The GS881E18//36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
The GS881E18/36T features ByteSafe data security functions.
See detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18//36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Rev: 1.10 9/2000
1/34
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS881E18/36T-11/11.5/100/80/66
TQFP Pin Descriptio
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
16
66
87
93, 94
95, 96
95, 96
89
88
98
97
86
83
84, 85
Symbol
A
0
, A
1
A
2
–A
17
A
18
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
NC
DP
QE
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
E
2
G
ADV
ADSP, ADSC
Typ
e
I
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs
Data Input and Output pins ( x36 Version)
I/O
I/O
Data Input and Output pins
Data Input and Output pins
—
I
O
I
I
I
—
I
I
I
I
I
I
I
No Connect
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low ( x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Rev: 1.10 9/2000
4/34
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS881E18/36T-11/11.5/100/80/66
Pin Location
64
14
31
38
39
42
43
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
Symbol
ZZ
FT
LBO
TMS
TDI
TDO
TCK
V
DD
V
SS
V
DDQ
Typ
e
I
I
I
I
I
O
I
I
I
I
Description
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.10 9/2000
5/34
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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