NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Connection Diagrams
PLCC Pin Configuration
CE
XX/V
PP
NC
V
CC
XX/PGM
NC
A
15
A
14
7
O
12
O
11
O
10
O
9
O
8
GND
NC
O
7
O
6
O
5
O
4
17
6 5 4 3 2
8
9
10
11
12
13
14
15
16
1
44 43 42 41 40
38
37
36
35
34
33
32
31
30
39
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
29
O
12
O
11
O
10
O
9
O
8
GND
NC
O
7
O
6
O
5
O
4
1
CE
XX/V
PP
NC
V
CC
XX/PGM
NC
A
15
A
14
33
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
23
32
31
30
29
28
27
26
25
24
O
13
O
14
O
15
44 43 42 41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
9
10
18 19 20 21 22 23 24 25 26 27 28
O
3
O
2
O
1
O
0
OE
NC
A
0
A
1
A
2
A
3
A
4
12 13 14 15 16 17 18 19 20 21 22
11
O
3
O
2
O
1
O
0
OE
NC
A
0
A
1
A
2
A
3
A
4
Top View
DS011376-3
O
13
O
14
O
15
DS011376-7
Commercial Temperature Range
(0°C to +70°C) V
CC
= 3.3V
±
0.3
Parameter/Order Number
NM27LV210 V 200
NM27LV210 V 250
Extended Temperature Range
(-40°C to +85°C) V
CC
= 3.3V
±0.3
Parameter/Order Number
NM27LV210 VE 250
• All packages conform to JEDEC standard.
• All versions are guaranteed to function in slower applica-
tions.
Access Time (ns)
200
250
Access Time (ns)
250
Pin Names
A0–A15
CE
OE
O0–O15
PGM
XX
NC
V
PP
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
No Connect
Programming Voltage
• Consult the FSC representative for newly released products/
packages.
2
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
Absolute Maximum Ratings
(Note 2)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground (Note 12)
V
PP
and A9 with Respect to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
-65°C to +150°C
All Output Voltages with
Respect to Ground (Note 11)
V
CC
+ 1.0V to GND - 0.6V
Operating Range
-0.6V to +7V
-0.6V to +14V
-0.6V to +7V
>2000V
Range
Commercial
Extended
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
3.3
3.3
Tolerance
±0.3
±0.3
DC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
I
SB1
I
SB2
I
CC
I
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage (TTL)
Output High Voltage (TTL)
Output Low Voltage (CMOS)
Output High Voltage (CMOS)
V
CC
Standby Current (TTL)
V
CC
Standby Current (CMOS)
V
CC
Active Current
V
PP
Supply Current
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.3
2.0
Max
0.7
V
CC
+ 0.3
0.4
Units
V
V
V
V
2.4
0.2
V
CC
- 0.3
CE = V
IH
CE = V
CC
±0.3V
CE = OE = V
IL
,
I/O = 0
µA
V
PP
= V
CC
V
IN
= 3.3 or GND
V
OUT
= 3.3V or GND
-1
-1
f = 5 MHz
150
50
20
10
1
10
V
V
µA
µA
mA
µA
µA
µA
AC Read Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 3)
t
OH
(Note 3)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Output Hold from Addresses,
CE or OE , Whichever
Occurred First
0
200
Max
200
200
70
50
0
250
Min
Max
250
250
75
60
Units
ns
0
0
Capacitance (Note 3)
T
A
= +25˚C, f = 1 MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
12
13
Max
20
20
Units
pF
pF
3
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NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 9)
≤5
ns
0.45V to 2.4V
0.8V and 2V
0.8V and 2V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
AC Waveforms
(Note 7) (Note 8) (Note 10)
ADDRESS
2.0V
0.8V
2.0V
0.8V
Address Valid
CE
OE
2.0V
0.8V
OUTPUT
2.0V
0.8V
Hi-Z
t ACC
(Note 3)
Note 2:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 3:
This parameter is only sampled and is not 100% tested.
Note 5:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
™
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 6:
TRI-STATE may be attained using OE or CE.
Note 7:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 8:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 9:
1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
: 100 pF includes fixture capacitance.
Note 10:
V
PP
may be connected to V
CC
except during programming.
Note 11:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 4:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
,
,,
t CF
t CE
(Note 4, 5)
t DF
t OE
(Note 4, 5)
(Note 3)
Valid Output
Hi-Z
t DH
DS011376-4
Programming Characteristics
(Note 12) (Note 13) (Note 14) (Note 15)
Symbol
t
AS
t
OES
t
CES
t
DS
t
VPS
t
VCS
t
AH
t
DH
t
DF
Parameter
Address Setup Time
OE Setup Time
CE Setup Time
Data Setup Time
V
PP
Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Conditions
Min
1
1
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
µs
OE = V
IH
1
1
1
1
0
1
CE = V
IL
0
60
ns
4
www.fairchildsemi.com
NM27LV210 1,048,576-Bit (64K x 16) Low Voltage EPROM
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