FX-427
Low Jitter Frequency Translator
Features
•
Quartz-based PLL for Ultra-Low Jitter
•
Frequency Translation up to 850 MHz
•
Accepts 4 externally-muxed clock inputs
•
LVCMOS/LVDS/LVPECL Inputs Compatible
•
Differential LVPECL Outputs
•
Lock Detect
•
Output Disable
•
20.3 x 13.7 x 5.1 mm surface mount package
•
Compliant to EC RoHS Directive
Description
The FX-427 is a precision quartz-based frequency
translator used to translate 1 to 4 selected input
clocks as low as 8 kHz to an integer multiple as
high as 850 MHz. The FX-427’s superior jitter
performance is achieved through the filtering action
of the on-board voltage-controlled SAW oscillator
(VCSO) and integrated loop filter. Two low-jitter
outputs are provided. Monitoring and control
functionality are also standard features.
Applications
•
Wireless Infrastructure
•
802.16 BTS
•
10 Gigabit FC
•
10GbE LAN / WAN
•
OADM and IP Routers
•
Test Equipment
Figure 1. Functional Block Diagram
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 1 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 8Nov06
FX-427 Low Jitter Frequency Translator
Table 1. Electrical Performance
Parameter
Frequency
Input Frequency
Capture Range
Output Frequency - Primary
Output Frequency - Secondary
F
IN
APR
F
OUT1
F
OUT2
V
CC
I
CC
F
IN
F
IN
F
IN
V
OCM
V
OH
V
OL
V
P-P
t
R
t
F
SYM
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
J
Φ
J
T
OP
V
CC
-1.5
V
CC
-1.085
V
CC
-1.830
0.008
±40
500
125
3.13
3.3
140
CMOS
LVDS
LVPECL
V
CC
-1.3
V
CC
-0.950
V
CC
-1.700
700
0.5
0.5
50
-64/-27
-95/-55
-123/-85
-143/-110
-146/-130
-146/-146
-146/-146
0.30
0.12
0° to 70° or -40 to +85°
V
CC
-1.1
V
CC
-0.880
V
CC
-1.620
V
V
V
mV-pp
ns
ns
%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps RMS
ps RMS
°C
200
850
850
3.46
180
MHz
ppm
MHz
MHz
V
mA
1,2,3
1,2,3
1,2,3
1,2,3
2,3
3
Symbol
Minimum
Typical
Maximum
Units
Notes
Supply
Voltage
Current (No Load)
Input Signal
CMOS
LVDS
LVPECL
2,3
Differential Output (Options
F
and
P)
Common Mode Output Voltage
DC Output High Voltage
DC Output Low Voltage
Peak-to-Peak Output Voltage
Rise Time
Fall Time
Symmetry
SSB Phase Noise,
F
OUT
=
155.52/622.08
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
Jitter Generation
155.52 MHz (12 kHz – 20 MHz BW)
622.08 MHz (12 kHz – 20 MHz BW)
45
55
3,5
3,5
3,5
3,5
4,5
4,5
2,3
5,6
5, 6
1,3
Operating Temperature (Options
C
or
F)
1.
2.
3.
4.
5.
6.
See Standard Frequencies and Ordering Information.
Parameters are tested with production test circuit below (Fig 2).
Parameters are tested at ambient temperature with test limits guard banded for specified operating temperature.
Measured from 20% to 80% of a full output swing (Fig 3).
Not tested in production, guaranteed by design, verified at qualification.
The FX-427 phase noise and jitter performance can be optimized for specific applications. Please consult with Vectron’s Application
Engineers for more information.
Figure 2. Test Circuit
Figure 3. LVPECL Waveform
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 2 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 8Nov06
FX-427 Low Jitter Frequency Translator
Figure 4. Pin Configuration
Table 2. Pin Out
Pin #
1
2
3
4
5
Symbol
SEL0
SEL1
GND
I/O
I
I
GND
Level
LVCMOS
LVCOMS
Supply
Function
Frequency Select - see table 3
Frequency Select – see table 3
Case and Electrical Ground
Not present
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input
frequency may be out of range if the voltage exceeds these levels.
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Lock Detect
Locked = Logic “1”
Loss of Lock = Logic “0”
Frequency Output – Primary
Complimentary Frequency Output - Primary
Divided-Down VCSO/VCXO Output, or Disabled
Complimentary Divided-Down VCSO/VCXO Output, or Disabled
Case and Electrical Ground
Input Frequency – AC Coupled
Power Supply Voltage (3.3 V ±5%)
VMON
O
Analog
(0 – Vcc)
LVCMOS
6
OD
I
7
8
9
10
11
12
13
14
LD
FOUT1
CFOUT1
FOUT2
CFOUT2
GND
FIN
VCC
O
O
O
O
O
GND
I
VCC
LVCMOS
LCPECL
LVPECL
LVPECL
LVPECL
Supply
LVCMOS or
LVPECL
Supply
Table 3. Control Logic (LVCMOS)
SEL0
0
0
1
1
SEL1
0
1
0
1
CLOCK INPUT
FIN
1
FIN
2
FIN
3
FIN
4
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 3 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 8Nov06
FX-427 Low Jitter Frequency Translator
Outline Diagram
mm
[inches]
0.79
[0.031]
20.32
[0.800]
2.54
[0.100]
1
R0.51
[R0.020]
7
14
8
BOTTOM VIEW BOARD
1.73
[0.068]
14
1.73
[0.068]
2.54
[0.100]
8
13.72
[0.540]
12.70
[0.500]
TOP VIEW COVER
1
20.07
[0.790]
7
5.10
[0.201]
Figure 5.
ugg
Suggested Pad Layout
21.59
[0.848]
2.54
[0.100]
14
KEEP OUT AREA
NO CIRCUITRY
UNDER HERE
1
3.05
[0.120]
1.90
[0.075]
Figure 6.
8
9.40
[0.369]
7
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 4 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 8Nov06
FX-427 Low Jitter Frequency Translator
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temp/Time
Symbol
V
CC
TS
T
LS
Ratings
0 to 6
-55 to 125
260/40
Unit
V
°C
°C/sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is
not implied at these or any other conditions in excess of conditions represented in the operational sections of this
data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR
reflow simulation. The FX-427 family is undergoing the following qualification tests:
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the FX-427 proper precautions should be taken when
handling and mounting. VI employs a human body model (HBM) and a charged-device model (CDM) for ESD
susceptibility testing and design protection evaluation
ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
500 V
500 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 5 of 8
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 8Nov06
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