Package Power Dissipation ..............................
see graph
Operating Temperature Range (T
A
) ....... –55°C to +125°C
Storage Temperature Range (T
S
) .......... –65°C to +150°C
Note 1:
Note 2:
Note 3:
T
A
= 25°C
Derate at the rate of 20mW/°C above T
A
= 25°C.
Micrel CMOS devices have input-static protection but are
susceptible to damage when exposed to extremely high static
electrical charges.
Allowable Duty Cycles
Number of
Outputs ON at
I
OUT
= –200 mA
8
7
6
5
4
3
2
1
Max. Allowable Duty Cycles
at T
A
of:
50°C
53%
60%
70%
83%
100%
100%
100%
100%
60°C
47%
54%
64%
75%
94%
100%
100%
100%
70°C
41%
48%
56%
67%
84%
100%
100%
100%
Electrical Characteristics
V
BB
= 50V, V
DD
= 5V to 12V; T
A
= +25°C; unless noted.
Limits
Characteristic
Output Leakage Current
Output Saturation Voltage
Symbol
I
CEX
V
CE(SAT)
V
BB
50V
50V
Test Conditions
T
A
= +25°C
T
A
= +85°C
I
OUT
= –100mA, T
A
= +85°C
I
OUT
= –225mA, T
A
= +85°C
I
OUT
= –350mA, T
A
= +85°C
Output Sustaining Voltage
Input Voltage
V
CE(SUS)
V
IN(1)
V
IN(0)
Input Current
Input Impedance
Maximum Clock Frequency
Serial Data Output Resistance
Turn-On Delay
Turnoff Delay
Supply Current
I
IN(1)
Z
IN
f
c
R
OUT
t
PLH
t
PHL
I
BB
I
DD
50V
50V
50V
50V
50V
50V
50V
50V
50V
50V
50V
V
DD
= 5.0V
V
DD
= 12V
Output Enable to Output, I
OUT
= –350mA
Output Enable to Output, I
OUT
= –350mA
all outputs on, all outputs open
all outputs off
V
DD
= 5V, all outputs off, inputs = 0V
V
DD
= 12V, all outputs off, inputs = 0V
V
DD
= 5V, one output on, all inputs = 0V
V
DD
= 12V, one output on, all inputs = 0V
Diode Leakage Current
Diode Forward Voltage
I
H
V
F
Max
Open
T
A
= +25°C
T
A
= +85°C
I
F
= 350mA
Note 4:
Positive (negative) current is defined as going into (coming out of) the specified device pin.
Note 5:
Operation of these devices with standard TTL may require the use of appropriate pull-up resistors.
Min.
Max.
–50
–100
1.8
1.9
2.0
Units
µA
µA
V
V
V
V
V
V
V
µA
µA
kΩ
kΩ
MHz
I
OUT
= –350mA, L = 2mH
V
DD
= 5.0V
V
DD
= 12V
V
DD
= 5V to 12V
V
DD
= V
IN
= 5.0V
V
DD
= 12V
V
DD
= 5.0V
V
DD
= 12V
35
3.5
10.5
V
SS
–0.3
V
DD
+0.3
V
DD
+0.3
0.8
50
240
100
50
3.3
20
6.0
2.0
10
10
200
100
200
1.0
3.0
50
100
2.0
kΩ
kΩ
µs
µs
mA
µA
µA
µA
mA
mA
µA
µA
V
May 2006
3
MIC5891
MIC5891
Micrel, Inc.
Timing Conditions
A.
B.
C.
D.
E.
F.
G.
H.
I.
(V
DD
= 5.0V, Logic Levels are V
DD
and Ground)
Minimum data active time before clock pulse (data set-up time).........................................................................75ns
Minimum data active time after clock pulse (data hold time) ...............................................................................75ns
Minimum data pulse width .................................................................................................................................150ns
Typical time between strobe activation and output transition .............................................................................1.0µs
Turnoff delay ................................................................................................................. see Electrical Characteristics
Turn-on delay................................................................................................................ see Electrical Characteristics
CLOCK
A
DATA IN
B
D
E
F
C
STROBE
OUTPUT
ENABLE
G
OUT N
H
I
Timing Conditions
MIC5891
4
May 2006
MIC5891
Micrel, Inc.
Truth Table
Serial
Data
Input
H
L
X
Clock
Input
Shift Register Contents
I
1
H
L
X
P
1
I
2
I
3
…
I
N-1
I
N
Serial
Data Strobe
Output Input
R
N-1
R
N-1
R
N
X
P
N
L
H
R
1
R
2
R
3
… R
N-1
R
N
P
1
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Latch Contents
I
1
I
2
I
3
… I
N-1
I
n
Output
Enable
Output Content
I
1
I
2
I
3
… I
N-1
I
n
R
1
R
2
R
1
R
2
X
P
2
X
P
3
… R
N-2
R
N-1
… R
N-2
R
N-1
… R
N-1
R
N
…
X
X
… P
N-1
P
N
R
1
R
2
R
3
P
2
X
P
3
X
… P
N-1
P
N
…
X
X
L
H
P
1
P
2
P
3
… P
N-1
P
N
L
L
L … L
L
Applications Information
Serial data present at the input is transferred into the shift
register on the rising edge of the CLOCK input pulse. Additional
CLOCK pulses shift data information towards the SERIAL
DATA OUTPUT. The serial data must appear at the input prior
to the rising edge of the CLOCK input waveform.
The 8 bits present in the shift register are transferred to the
respective latches when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Most applications where the
latching feature is not used (STROBE tied high) require the
OUTPUT ENABLE input to be high during serial data entry.
Outputs are active (controlled by the latch state) when the
OUTPUT ENABLE is low. All Outputs are low (disabled) when
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
