ADVANCED INFORMATION
MX67L12816J3/MX67L9632J3
32M-BIT [4Mb x 8 or 2Mb x 16] Flash Plus 96M-BIT [12Mb x 8 or 6Mb x 16] MTP CMOS,
16M-BIT [2Mb x 8 or 1Mb x 16] Flash Plus 128M-BIT [16Mb x 8 or 8Mb x 16] MTP CMOS
Flash Plus MTP MonoChip
FEATURES
• 2.7V to 3.6V operation voltage (Output power supply
1.65V-1.95V or 2.7V-3.6V through VCCQ pin)
• Separate banks for data and code
- MX67L9632J3:
32Mb(x8/x16) Flash Bank for data
96Mb(x8/x16) MTP Bank for code
- MX67L12816J3:
16Mb(x8/x16) Flash Bank for data
128Mb(x8/x16) MTP Bank for code
• Block Structure
- Flash Bank of MX67L9632J3
Thirty-two 128K byte blocks
- MTP Bank of MX67L9632J3
Ninety-six 128K byte blocks
- Flash Bank of MX67L12816J3
Sixteen 128K byte blocks
- MTP Bank of MX67L12816J3
Hundred and Twenty-eight 128K byte blocks
• Fast random / page mode access time
- 150/25 ns Read Access Time
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 32-Byte Write Buffer
- 6 us/byte Effective Programming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
• Operation Temperature:-40° to 85°
C
C
Buffer Command)
• Program/Erase Cycles
- MX67L12816J3
- 160K Total Min. Erase Cycle (for Flash Bank)
- 10K Minimum Erase Cycles per Block
- 128K Total Min. Erase Cycle for MTP Bank
- 1,000 Minimum Erase Cycles per block
- MX67L9632J3
- 320K Total Min. Erase Cycle (for Flash Bank)
- 10K Minimum Erase Cycles per Block
- 96K Total Min. Erase Cycle for MTP Bank
- 1,000 Minimum Erase Cycles per block
SOFTWARE FEATURE
• Suppor t Common Flash Interface (CFI) (for
MX67L9632J3)
- Flash device parameters stored on the device and
provide the host system to access.
• Automation Suspend Options
- Block Erase Suspend to Read
- Block Erase Suspend to Program
- Program Suspend to Read
HARDWARE FEATURE
• A0 pin
- Select low byte address when device is in byte mode.
Not used in word mode.
• STS pin
- Indicates the status of the internal state machine.
• VPEN pin
- For Erase /Program/ Block Look enable.
• VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
PERFORMANCE
• Low power dissipation
- 10mA active current
- 50uA standby current
- 5uA deep power-down current
• High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
PACKAGING
- 56-Lead TSOP
- 64-ball Flip Chip CSP
TECHNOLOGY
- 0.25u 2bits per cell NBit Flash Technology
P/N:PM0904
REV. 0.2, NOV. 22, 2002
1
MX67L12816J3/MX67L9632J3
GENERAL DESCRIPTION
The MX67L9632J3 is a single chip which consists of a
32M bit Flash and a 96M bit MTP EPROM ;
MX67L12816J3 is a single chip which consists of a 16M
bit Flash and a 128M bit MTP EPROM. The MX67L9632J3
organized as a 32Mb(x8/x16) flash bank and a 96Mb(x8/
x16) MTP bank; the MX67L12816J3 organized as a
16Mb(x8/x16) flash bank and a 128Mb(x8/x16) MTP bank.
MXIC's Flash plus MTP MonoChip offers the most cost-
effective and reliable read/write non-volatile random ac-
cess memory. The MX67L12816J3 and MX67L9632J3
are packaged in 56 pin TSOP and 64-ball CSP. It is de-
signed to be reprogrammed and erased in system or in
standard EPROM programmers.
The standard MX67L12816J3 & MX67L9632J3 offers ran-
dom access time as fast as 120ns and page mode read
as fast as 25ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus conten-
tion, the MX67L12816J3 & MX67L9632J3 has three sepa-
rate chip enable (CE0, CE1, and CE2) and output enable
OE controls. MXIC’s MonoChip augment EPROM func-
tionality with in-circuit electrical erasure and program-
ming. The MX67L12816J3 & MX67L9632J3 uses a com-
mand register to manage this functionality.
MXIC's MonoChip technology reliably stores memory con-
tents even after 10,000 erase and program cycles for
Flash bank and 1,000 cycles for MTP bank. The MXIC
cell is designed to optimize the erase and program
mechanisms by utilizing the dielectric's character to trap
or release charges from ONO layer.
The MX67L12816J3 & MX67L9632J3 uses a 2.7V to 3.6V
VCC supply to perform the High Reliability Erase and
auto Program/ Erase algorithms. The highest degree of
latch-up protection is achieved with MXIC’s proprietary
non-epi process. Latch-up protection is proved for
stresses up to 100 milliamps on address and data pin
from -1V to VCC +1V.
PIN CONFIGURATION
56 TSOP(14mm x 20mm)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RESET
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A24*
WE
OE
STS
Q15
Q7
Q14
Q6
GND
Q13
Q5
Q12
Q4
VCCQ
GND
Q11
Q3
Q10
Q2
VCC
Q9
Q1
Q8
Q0
A0
BYTE
A23
CE2
Notes:
1. A24 exists on MX67L12816J3. The pin is a no connect (NC) on MX67L9632J3.
P/N:PM0904
REV. 0.2, NOV. 22, 2002
2
MX67L12816J3/MX67L9632J3
64 ball Easy BGA (10x13x1.2mm, 1.0mm-ball pitch)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VCC
A18
A22
B
A2
GND
A9
CE0
A14
DU
A19
CE1
C
A3
A7
A10
A12
A15
DU
A20
A21
D
A4
A5
A11
RESET
DU
DU
A16
A17
E
Q8
Q1
Q9
Q3
Q4
DU
Q15
STS
13 mm
F
BYTE
Q0
Q10
Q11
Q12
DU
DU
OE
G
A23
A0
Q2
VCCQ
Q5
Q6
Q14
WE
H
CE2
DU
VCC
GND
Q13
GND
Q7
A24*
10mm
Notes:
1. Address A24 is only valid on MX67L12816J3. Otherwise, it is a no connect (NC).
2. Don't Use (DU) pins refer to pins that should not be connected.
PIN DESCRIPTION
SYMBOL
A0
A1~A24
Q0~Q15
WE
OE
RESET
STS
BYTE
VPEN
VCCQ
VCC
GND
NC
DU
P/N:PM0904
PIN NAME
Byte Select Address
Address Input (MX67L9632J3:A0~A23,
MX67L12816J3:A0~A24)
Data Inputs/Outputs
Write Enable Input
Output Enable Input
Reset/Deep Power Down mode
STATUS Pin
Byte Mode Enable
ERASE/PROGRAM/BLOCK Lock
Enable
Output Buffer Power Supply
Device Power Supply
Device Ground
Pin Not Connected Internally
Don't Use
REV. 0.2, NOV. 22, 2002
CE0, CE1, CE2 Chip Enable Input
3
MX67L12816J3/MX67L9632J3
BLOCK DIAGRAM
CE0
CE1
CE2
OE
WE
RESET
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
Flash
ARRAY
MTP
ARRAY
ARRAY
SOURCE
HV
STATE
REGISTER
X-DECODER
ADDRESS
LATCH
A0-A24
AND
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
P/N:PM0904
REV. 0.2, NOV. 22, 2002
4
MX67L12816J3/MX67L9632J3
FIGURE 1. Block Architecture
Flash memory reads erases and writes in-system via the local CPU. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
A[23-0]: MX67L9632J3
FFFFFF
FE0000
128-Kbyte Block
127
A[23-1]: MX67L9632J3
7FFFFF
7F0000
64-Kword Block
127
32 Mbit
Flash bank
.
.
.
BFFFFF
BE0000
128-Kbyte Block
95
5FFFFF
5F0000
.
.
.
64-Kword Block
95
.
.
.
03FFFF
020000
01FFFF
000000
128-Kbyte Block
128-Kbyte Block
1
0
01FFFF
010000
00FFFF
000000
.
.
.
64-Kword Block
64-Kword Block
1
0
96 Mbit
MTP bank
Byte Mode (x8)
Word Mode (x16)
A[24-0]: MX67L12816J3
11FFFFF
11E0000
128-Kbyte Block
143
A[24-1]: MX67L12816J3
8FFFFF
8F0000
64-Kword Block
143
16 Mbit
Flash bank
.
.
.
FFFFFF
FE0000
128-Kbyte Block
127
7FFFFF
7F0000
.
.
.
64-Kword Block
127
.
.
.
03FFFF
020000
01FFFF
000000
128-Kbyte Block
128-Kbyte Block
1
0
01FFFF
010000
00FFFF
000000
.
.
.
64-Kword Block
64-Kword Block
1
0
128 Mbit
MTP bank
Byte Mode (x8)
Word Mode (x16)
P/N:PM0904
REV. 0.2, NOV. 22, 2002
5
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