INDEX
NEW ADVANCED INFORMATION
MX29F001T/B
1M-BIT [128K x 8]CMOS FLASH MEMORY
FEATURES
• 131072x8 only organization
• Fast access time: 70/90/120ns
• Low power consumption
– 30mA maximum active current
– 1µ
A
typical standby current
• Command register architecture
– Byte Programming (7µs typical)
– Block Erase (8K-Byte x1, 4K-Byte x 2, 8K Bytex2,
32K-Bytex1, and 64K-Byte x1)
• Auto Erase (chip & block) and Auto Program
– Automatically erase any combination of sectors
with Erase Suspend capability.
– Automatically programs and verifies data at speci
fied address
• Erase Suspend/Erase Resume
– Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
• Status Reply
– Data polling & Toggle bit for detection of program
and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V
system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
– T = Top Boot Sector
– B = Bottom Boot Sector
• Low VCC write inhibit≤ 3.2V
• Package type:
– 32-pin PLCC
– 32-pin TSOP
– 32-pin PDIP
• Boot Code Sector Architecture
– T=Top Boot Sector
– B=Bottom Boot Sector
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX29F001T/B is packaged in 32-pin PLCC, TSOP,
PDIP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
The standard MX29F001T/B offers access time as
fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX29F001T/B has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and
fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX29F001T/B uses a 5.0V
±
10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0515
1
REV. 1.7, SEP 14, 1998
INDEX
MX29F001T/B
PIN CONFIGURATIONS
32 PDIP
A12
A15
A16
PIN DESCRIPTION:
32PLCC
VCC
WE
NC
NC
SYMBOL
A0~A16
A14
A13
A8
A9
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
Q1
Q2
Q3
Q4
Q5
TSOP (TYPE 1)
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
GND
Q6
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
A7
A6
A5
A4
A3
A2
A1
A0
Q0
5
4
1
32
30
29
Q0~Q7
CE
WE
OE
VCC
GND
MX29F001T/B
9
MX29F001T/B
25
A11
OE
A10
CE
13
14
17
21
20
Q7
BLOCK STRUCTURE
A16~A0
1FFFFH
1DFFFH
1CFFFH
1BFFFH
19FFFH
17FFFH
0FFFFH
00000H
8
4
4
8
8
32
64
K-BYTE
K-BYTE
K-BYTE
K-BYTE
K-BYTE
K-BYTE
K-BYTE
MX29F001T/B
(NORMAL TYPE)
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F001T/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
MX29F001T Sector Architecture
A16~A0
1FFFFH
0FFFFH
07FFFH
05FFFH
03FFFH
02FFFH
8
8
4
4
8
00000H
K-BYTE
K-BYTE
K-BYTE
K-BYTE
K-BYTE
64
32
K-BYTE
K-BYTE
(REVERSE TYPE)
01FFFH
MX29F001B Sector Architecture
P/N: PM0515
REV. 1.7, SEP 14, 1998
2
INDEX
MX29F001T/B
BLOCK DIAGRAM
CE
OE
WE
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
MX29F001T/B
X-DECODER
REGISTER
ARRAY
SOURCE
HV
ADDRESS
LATCH
A0-A16
FLASH
ARRAY
AND
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
P/N: PM0515
REV. 1.7, SEP 14, 1998
3
INDEX
MX29F001T/B
AUTOMATIC PROGRAMMING
The MX29F001T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical
chip programming time of the MX29F001T/B at room
temperature is less than 2 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29F001T/B electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron
injection.
During a program cycle, the state-machine will control the
program sequences and command register will not re-
spond to any command set. During a Sector Erase cycle,
the command register will only respond to Erase Suspend
command. After Erase Suspend is completed, the device
stays in read mode. After the state machine has com-
pleted its task, it will allow the command register to
respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase
pulses according to MXIC's Automatic Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than two second. The Automatic
Erase algorithm automatically programs the entire
array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.
AUTOMATIC BLOCK ERASE
The MX29F001T/B is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes allow
blocks of the array to be erased in one erase cycle.
The Automatic Block Erase algorithm automatically
programs the specified block(s) prior to electrical
erase. The timing and verification of electrical erase
are internally con trolled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires
the user to only write program set-up commands
(include 2 unlock write cycle and A0H) and a program
command (program data and address). The device
automatically times the programming pulse width,
provides the program verification, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provides feedback to the user as to the
status of the programming operation.
P/N: PM0515
REV. 1.7, SEP 14, 1998
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INDEX
MX29F001T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
Bus
Cycle
Reset/Read
Reset/Read
Read Silicon ID
Chip Protect Verify
1
4
4
4
First Bus
Cycle
Addr
Data
Second Bus
Cycle
Addr
Data
Third Bus
Cycle
Addr
Data
Fourth Bus
Cycle
Addr
Data
Fifth Bus
Cycle
Addr Data
Sixth Bus
Cycle
Addr Data
XXXH F0H
555H AAH
555H AAH
555H AAH
2AAH 55H
2AAH 55H
2AAH 55H
555H
555H
555H
F0H
90H
90H
RA
ADI
SA
x02
RD
DDI
00H
01H
PD
2AAH
2AAH
55H 555H 10H
55H
SA
30H
Porgram
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for sector
protect/unprotect
4
6
6
1
1
6
555H AAH
555H AAH
555H AAH
XXXH B0H
XXXH 30H
555H AAH
2AAH 55H
2AAH 55H
2AAH 55H
555H A0H
555H
555H
80H
80H
PA
555H AAH
555H AAH
2AAH 55H
555H
80H
555H AAH
2AAH 55H
555H 20H
Note:
1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to
Table 3)
DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A16 in either state.
4.For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data is
00H, it means the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register com-
mand sequences. Note that the Erase Suspend (B0H)
and Erase Resume (30H) commands are valid only
while the Sector Erase operation is in progress. Either
of the two reset command sequences will reset the
device(when applicable).
P/N: PM0515
REV. 1.7, SEP 14, 1998
5
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