U s e r ’ s M a n u a l , V 3. 0 , F e b . 2 00 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2001-02
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
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U s er ’ s M a n u a l , V 3. 0 , F e b . 2 00 1
C161CS-32R/-L
C161JC-32R/-L
C161JI-32R/-L
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C161CS/JC/JI
Revision History:
Previous Version:
Page
all
1-2
2-21
3-4
4-2
5-29
6-9
6-10
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7-8
7-14
7-31
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7-34
7-48
9-6
9-22, 9-23
9-28
9-31, 9-32
9-33
9-35, 9-36
9-37ff
10-6, 10-27
10-16, 10-33
10-30
10-36
11-13, 11-14
13-5
13-13
14-2
14-5, 14-6
16-2, 16-3
16-7
V3.0, 2001-02
2001-01 V2.0 (intermediate version)
1999-05 V1.0
Subjects (major changes since last revision)
1)
Converted to new company layout, figures have been redrawn
List of derivatives enhanced
List of protected bits enhanced
XBUS areas corrected
Sleep mode added
Interrupt source control enhanced
Frequency table adapted
Description of PLL base frequency improved
Bit P4LIN added
Description of temperature compensation removed
Description of PORT0 control corrected
Description of BHE during bus hold corrected
ODP4 enhanced
Description of alternate Port 4 functions corrected
CAN/SDLM interface functions added
Note reworked
Bits BSWCx and EWENx added to register BUSCONx
Note corrected
Description of bus arbitration improved
Description of BHE during bus hold corrected
Section “Connecting Bus Masters” improved
XBUS interface description improved
Table enhanced
Figure corrected
Description of T5M corrected
CT3 function added to figure
Tables enhanced
Description of transmission timing improved
Baudrate tables improved
Clock path in figure corrected
Time range table and reset source table improved
Description of BSL entry improved
Baudrate table added
C161CS/JC/JI
Revision History:
Previous Version:
Page
17-7
17-14
18-4
19-1
19-11
20-5, 20-9
20-10
20-12
20-25ff
20-43
21-1
21-3
21-4
22-13
22-18
22-19
22-22
22-23
23-2
23-21
23-22ff
24-5
25-3
25-4ff
1)
V3.0, 2001-02
(cont’d)
2001-01 V2.0 (intermediate version)
1999-05 V1.0
Subjects (major changes since last revision)
1)
Frequency table enhanced
Description improved (2nd paragraph)
Sample time control added
Port 7 added
Bit timing section rearranged
Description improved
Description of TXINCE corrected
Description improved (lower half)
Several bit-descriptions improved
Location of RXCNTB corrected
Port 9 added
Clock count n and BRP value corrected
Figure improved
Figure corrected
Software configuration introduced (see notes)
Table enhanced for 33 MHz
Code example corrected
Address space for RSTCON corrected
SYSCON1 added (3
rd
paragraph)
Frequency range table improved
Description of security mechanism and SW examples reworked
Linear stack size corrected
Offset of RH7 corrected
P5DIDIS, RSTCON added, SDLM registers added
These changes refer to version V1.0, 1999-05.
Controller Area Network (CAN): License of Robert Bosch GmbH
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