Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to
the Recommended Operating Conditions.
2
Parametric values specified at:
−4.2
to 5.46V
DC CHARACTERISTICS
(V
CC
= V
CCO
= GND; V
EE
=
−4.2
to 5.46V)
0°C
Symbol
V
OH
V
OL
V
OHA
V
OLA
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
Characteristic
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Reference Voltage
Input HIGH Current
Input LOW Current
Supply Current
0.5
61
122
−1165
−1810
−1380
Min
−1025
−1810
−1035
−1610
−880
−1475
−1260
200
0.5
61
122
−1165
−1810
−1380
Typ
−955
−1705
Max
−880
−1620
Min
−1025
−1810
−1035
−1610
−880
−1475
−1260
200
0.5
70
141
−1165
−1810
−1380
25°C
Typ
−955
−1705
Max
−880
−1620
Min
−1025
−1810
−1035
−1610
−880
−1475
−1260
200
85°C
Typ
−955
−1705
Max
−880
−1620
Unit
mV
mV
mV
mV
mV
mV
V
μA
μA
mA
Condition
V
in
= V
IH(max)
or V
IL(min)
V
in
= V
IH(max)
or V
IL(min)
V
in
= V
IH(max)
or V
IL(min)
V
in
= V
IH(max)
or V
IL(min)
1. 100SX circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. All outputs are loaded with 50Ω to V
CC
−
2V.
AC CHARACTERISTICS
(V
CC
= V
CCO
= GND; V
EE
=
−4.2
to 5.46V)
0 to 85°C
Symbol
F
max
t
pd
Propagation CCLK
in
to CCLK
out
Delay
CCLK
in
to QCMI
DCLK
in
to DCLK
out
DCLK
in
to QBIN
CCLK
in
to DCLK
out
CCLK
in
to QBIN
DCLK
in
to QCMI
Setup Time
Hold Time
BIN
in
to CCLK
in
CMI
in
to DCLK
in
CCLK
in
to BIN
in
DCLK
in
to CMI
in
250
−0.4
150
Note
700
Characteristic
Min
700
650
1000
550
1000
1100
800
−375
140
1000
120
1550
1750
1700
1800
2700
1700
ps
ps
mV
V
ps
20%
−
80%
Typ
Max
Unit
MHz
ps
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=‘L’, LBIN=‘H’
LCMI=‘L’, LBIN=‘L’
LCMI=‘H’, LBIN=‘L’
Add 3 CCLK
in
-Cycles to Delay
Add 4 DCLK
in
-Cycles to Delay
Add 3 CCLK
in
-Cycles to Delay
Add 5 DCLK
in
-Cycles to Delay
Condition
Notes
t
s
t
h
V
PP
V
CMR
t
r
, t
f
Minimum Input Swing
Common Mode Range
Rise/Fall Times
1. 100SX circuits are designed to meet the AC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range
and the peak-to-peak voltage lies between V
PP
min and 1V. The lower end of the CMR range is dependent on V
EE
and is equal to V
EE
+ 3.0V.
http://onsemi.com
3
MC100SX1230
Applications Information
CMI Code
The CMI code is a 1B2B code. Each information bit is
coded into two transmission bits. A binary 0 is coded to 01,
and a binary 1 is coded alternately to a 00 or a 11, thus
there is at least one transition during every bit period. A
typical data pattern is illustrated in the figure below.
Because of the coding, the data stream is not only DC
balanced, but it contains a rich clock component which aids
the clock recovery process at the receiver. A 2X clock is
used by the MC100SX1230 to ensure that the mid-bit
transition of the data 0 is ideally centered at the CMI
encoded output.
0
Binary
0
1
1
0
CMI
0
0
1
1
0
1.. CMI Code
Typical Application
In a traditional telecommunications application, the
MC100SX1230 is resident on the line card interface which
contains circuitry to implement the line transmitter and
receiver functions. On the decoder side, a cable
equalization filter followed by a clock recovery/decision
circuit are required to compensate for the cable attenuation
and distortion, extract the 2X clock signal and re-time the
CMI data. On the coder side, a PLL is required to
synthesize the 2X coder clock and a conditioning circuit is
needed at the output of the coder to generate the
appropriate signal to drive the cable.
Device Operation
The circuit contains a complete CMI coder and decoder
as well as the support circuitry necessary to perform loop
back of either the Binary input or the CMI input. The
operation is controlled by the LCMI and LBIN inputs. In
addition, the device generates an AIS (Alarm Indication
Signal) from the coder output when the binary loop back
state is active (LBIN=‘H’). The AIS signal indicates to the
receiver at the other end of the cable that ‘real’ data is not
being sent. The device contains a Reset input which should
normally be reset as part of the powering up sequence.
The coder accepts a differential data input (BIN
in
) as well
as a differential clock (CCLK
in
). The clock signal must be
twice the frequency of the input data signal, i.e. a 155 MBit/s
binary signal requires a 310 MHz clock, for proper
operation. Typical input and output waveforms are shown in
2.. The incoming clock signal is divided by 2 and
supplied at the coder clock output (CLK
out
). The BINin
signal is buffered before being driven into the input register
which clocks in the binary data. This results in a negative
setup time for the coder. The coded data is output from the
coder 3 CCLK
in
clock cycles plus normal propagation delay
after the binary data has been supplied.
The decoder accepts a differential data input (CMI
in
) as
well as a differential clock (DCLK
in
). The clock signal is
supplied from the external clock extraction circuit and runs
at the coded rate of either 280 MHz or 310 MHz depending
on weather the application is for a PDH system or an SDH
system. The decoder has a latency of 4 clock cycles so the
decoded data is output 4 cycles plus the normal
propagation delay after the input data is captured.
3.
illustrates the decoder operation.
Under certain conditions, the user may require that the
binary data to be coded be routed back to the output of the
decoder to verify proper system operation. This is accom-
plished through the use of the LBIN input control pin. When
this signal is asserted (LBIN = ‘H’), the BINin signal as well
as a divided by 2 version of the CCLKin input is routed to
the QBIN and DCLK
out
outputs respectively. The BINin to
QBIN output has a latency of 3 CCLK
in
cycles plus internal
propagation delays. In addition, the AIS signal is generated
and output from the QCMI output. To the receiver the AIS
signal is decoded as a constant logic ‘H’ signal. This
operation is seen in
4..
To complement the binary loop back feature, a CMI loop
back function is also supported. This is accomplished by
asserting the LCMI input control pin (LCMI =‘H’). Under this
condition, the CMI coded input is decoded, then routed
through the coder block to the QCMI output. The CMIin to
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