TITLE:
SPECIFICATION CONTROL DRAWING
X TEMPERATURE COEFFICIENT OF ATTEN. 1 X 10-3 DB/DB/°C.
SHIFT
(NEG)
-.003
-.004
-.005
-.006
-.007
-.009
PART IDENTIFIER:
MTVA0X00N0XW1
DB VALUE
1, 2, 3, 4, 5, 6, 7, 8
1, 2, 3, 4, 5, 6
1,2, 3, 4, 5, 6, 8
2, 3, 4, 6
2, 3, 4, 5, 6
3, 6
ATTENUATION SHIFT NEGATIVE.
X DB VALUE SEE TABLE ABOVE.
DESCRIPTION:
ASSEMBLY DWG:
1.0
TEMPERATURE VARIABLE CHIP ATTENUATOR
1900974
SPECIFICATIONS:
1.1
ELECTRICAL:
1.1.1
IMPEDANCE: 50 OHMS NOMINAL.
1.1.2
OPERATING FREQUENCY RANGE: DC - 12.4 GHZ.
1.1.3
ATTENUATION VALUES AVAILABLE: SEE ABOVE TABLE.
1.1.4
ATTENUATION ACCURACY AT 25°C:
±0.5DB
@ 1 GHZ.
1.1.5
VSWR: 1.30:1 MAX. @ 1GHZ.
1.1.6
INPUT POWER: 200 MILLIWATTS CW.
1.1.6.1 FULL RATED POWER TO 125°C, DERATED LINEARLY TO 0 WATTS AT 150°C.
1.1.7
TEMPERATURE COEFFICIENT OVER OPERATING TEMPERATURE RANGE:
SEE TABLE ABOVE, TEMPERATURE COEFFICIENT TOLERANCE: ±0.001 DB/DB/°C.
MECHANICAL:
1.2.1
OUTLINE DWG: SEE SHEET 2.
1.2.2
WORKMANSHIP: PER MIL-PRF-55342.
ENVIRONMENTAL:
1.3.1
OPERATING TEMPERATURE RANGE: -55°C TO +150°C.
ELECTROSTATIC DISCHARGE CONTROL: PER MIL-STD-1686.
NONE
1.2
1.3
1.4
2.0
3.0
UNIT MARKING:
QUALITY ASSURANCE:
3.1
SAMPLE INSPECT PER ANSI/ASQC Z1.4 GENERAL INSPECTION, LEVEL II, AQL = 1.0.
3.1.1
VISUAL AND MECHANICAL EXAMINATION FOR CONFORMANCE TO OUTLINE DRAWING REQUIREMENTS.
3.2
SAMPLE INSPECTION (DESTRUCTIVE TESTING).
3.2.1
SELECT THREE (3) UNITS FROM LOT AND MEASURE DCA EVERY 20°C OVER THE TEMPERATURE RANGE
-55°C TO +125°C.
3.2.1.1 CALCULATE, USING LINEAR REGRESSION, THE SLOPE OF THE CURVE.
3.2.1.2 CALCULATE TCA USING THE FOLLOWING FORMULA:
TCA =
SLOPE
.
ATTENUATION @ 25°C
3.2.1.3 ACCEPTANCE LIMITS: PER 1.1.7.
3.3
3.4
INSPECTION IN ACCORDANCE WITH 824W170 AND 824F036 FOR COMMERCIAL GRADE PRODUCT.
TEST DATA REQUIREMENTS:
3.4.1
NO TEST DATA REQUIRED FOR CUSTOMER.
3.4.2
DATA RETENTION - 24 MONTHS.
STANDARD PACK PER 755W002
4.0
PACKAGING:
EMC TECHNOLOGY
8851 SW OLD KANSAS AVE
STUART, FLORIDA 34997
423F006 REV.-
CAGE CODE # 24602
CHANGE NOTICE
EN 10-0911
DWG #
REV LVL
SHEET
1004865000
L
1
OF
2
FPGA/CPLD
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