TSPC106
PCI BRIDGE / MEMORY CONTROLLER
DESCRIPTION
The TSPC106 provides an integrated high–bandwidth, high–
performance, TTL–compatible interface between a 60x pro-
cessor, a secondary (L2) cache or additional (up to four total)
60x processors, the PCI bus, and main memory.
PCI support allows system designers to rapidly design sys-
tems using peripherals already designed for PCI.
The TSPC106 uses an advanced, 3.3-V CMOS process tech-
nology and maintains full interface compatibility with TTL devi-
ces.
The TSPC106 integrates in system testability and debugging
features through JTAG boundary-scan capability.
MAIN FEATURES
H
Processor bus frequency up to 66MHz and 83.3MHz.
H
64-bit data bus and 32-bit address bus.
H
L2 cache controle for 256-Kbyte, 512-Kbyte, 1-Mbyte sizes.
H
Provides support for either asynchronous SRAM, burst
SRAM, or pipelined burst SRAM.
G suffix
CBGA 303
Ceramic Ball Grid Array
H
Compliant with PCI specification, revision 2.1.
H
PCI interface operates at 20 to 33MHz, 3.3-volt/5.0-volt
compatible.
H
IEEE 1149.1-compliant, JTAG boundary-scan interface.
H
P
D
max = 1.7 watts (66Mhz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
GS suffix
CI–CGA 303
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H
MIL-STD-883 class Q or According to TCS standards
H
Upscreenings based upon TCS standards
Industrial temperature range
H
Full military temperature range (–55°C
≤
T
c
≤
+125°C)
(
–
40°C
≤
T
c
≤
+110°C)
H
V
CC
= 3.3 V
±
5 %.
H
303 pin CBGA packages and
303 pin CBGA with SCI (CI–CGA) package.
April 1999
1/40
TSPC106
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . 3
1.
2.
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. CBGA303 package . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2. Pinout listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
3.5.6.
Full-Power Mode . . . . . . . . . . . . . . . . . .
Doze Mode . . . . . . . . . . . . . . . . . . . . . . .
Nap Mode . . . . . . . . . . . . . . . . . . . . . . . .
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . .
Suspend Mode . . . . . . . . . . . . . . . . . . . .
Power dissipation . . . . . . . . . . . . . . . . . .
24
24
24
24
24
25
3.6. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10
3.1. 60x processor interface signals . . . . . . . . . . . . . . . 11
3.2. L2 Cache/Multiple processor interface signals .
3.2.1. Internal L2 controller signals . . . . . . . . .
3.2.2. External L2 controller signals . . . . . . . .
3.2.3. Multiple processor signals . . . . . . . . . . .
13
13
14
15
4.
ELECTRICAL CHARACTERISTICS . . . . . . . . . 26
4.1. General requirements . . . . . . . . . . . . . . . . . . . . . . 26
4.2. Static characteristics . . . . . . . . . . . . . . . . . . . . . . . 26
4.3. Dynamic characteristics . . . . . . . . . . . . . . . . . . . .
4.3.1. Clock AC specifications . . . . . . . . . . . . .
4.3.2. Input AC specifications . . . . . . . . . . . . .
4.3.3. Output AC specifications . . . . . . . . . . . .
26
27
28
29
3.3. Memory interface signals . . . . . . . . . . . . . . . . . . . 15
3.4. PCI interface signals . . . . . . . . . . . . . . . . . . . . . . . 17
3.5. Interrupt, clock and power management signals 19
3.6. IEEE 1149.1 interface signals . . . . . . . . . . . . . . . 20
3.7. Configuration signals . . . . . . . . . . . . . . . . . . . . . . 20
3.8. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9
Address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4. JTAG AC timing specifications . . . . . . . . . . . . . . 31
5.
FUNCTIONAL UNITS DESCRIPTION . . . . . . . . 33
5.1. 60x Processor Interface . . . . . . . . . . . . . . . . . . . . 33
5.2. Secondary (L2) Cache/Multiple Processor
Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3. Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4. PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.
SYSTEM DESIGN INFORMATION . . . . . . . . . . 34
6.1. PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . 35
6.3. Decoupling Recommendations . . . . . . . . . . . . . . 35
6.4. Connection Recommendations . . . . . . . . . . . . . . 35
6.4.1. Pull–up Resistor Recommendations . . 35
B. DETAILED SPECIFICATIONS . . . . . . . 22
1.
2.
3.
SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . 22
REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2. Design and construction . . . . . . . . . . . . . . . . . . . .
3.2.1. Terminal connections . . . . . . . . . . . . . .
3.2.2. Lead material and finish . . . . . . . . . . . .
3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
22
7.
PREPARATION FOR DELIVERY . . . . . . . . . . . . 36
7.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . 36
8.
9.
HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PACKAGE MECHANICAL DATA . . . . . . . . . . . . 37
9.1. BGA package description . . . . . . . . . . . . . . . . . . 37
9.1.1. Package parameters . . . . . . . . . . . . . . . 37
9.1.2. Mechanical dimensions of the BGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . 22
3.4. Thermal characteristics . . . . . . . . . . . . . . . . . . . . 23
3.4.1. Internal Package Conduction Resist. . 23
3.5. Power consideration . . . . . . . . . . . . . . . . . . . . . . . 24
10. ORDERING INFORMATION . . . . . . . . . . . . . . . 39
2/40
TSPC106
A. GENERAL DESCRIPTION
1. INTRODUCTION
The TSPC106 PCI bridge/memory controller (after named 106) provides a PowerPC
®
microprocessor common hardware reference
platform (CHRP
™
) compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect
(PCI) bus.
In this document, the term ‘60x’ is used to denote a 32–bit microprocessor from the PowerPC architecture family that conforms to the
bus interface of the PowerPC 601
®
, PowerPC 603
™
, or PowerPC 604
™
microprocessors. Note that this does not include the Pow-
erPC 602
™
microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is
specified for 32–bit addressing, which provides 32–bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and float-
ing–point data types of 32 and 64 bits (single–precision and double–precision).
The 106 provides an integrated high–bandwidth, high–performance, TTL–compatible interface between a 60x processor, a second-
ary (L2) cache or additional (up to four total) 60x processors, the PCI bus, and main memory. This section provides a block diagram
showing the major functional units of the 106 and describes briefly how those units interact.
Figure AUCUN LIEN shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show
the basic features rather than an attempt to show how these features are physically implemented on the device.
L2 Cache
Interface
L2
Memory
Memory
Interface
Power Management
60x Processor
Interface
60x Bus
Error/Interrupt
Control
Target
Master
Configuration
Registers
PCI Interface
PCI Bus
Figure 1 : Block Diagram
The 106 provides a PowerPC microprocessor CHRP–compliant bridge between the PowerPC microprocessor family and the PCI
bus. CHRP is a set of specifications that defines a unified personal computer architecture and brings the combined advantages of the
Power Macintosh platform and the standard PC environment to both system vendors and users. PCI support allows system design-
ers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces available in the personal
computer hardware environment. These open specifications make it easier for system vendors to design computers capable of run-
ning multiple operating systems. The 106 integrates secondary cache control and a high–performance memory controller. The 106
uses an advanced, 3.3–V CMOS process technology and is fully compatible with TTL devices.
The 106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x
address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor interface of the 106 uses a subset of the 60x bus
protocol, supporting single–beat and burst data transfers. The address and data buses are decoupled to support pipelined transac-
tions.
3/40
TSPC106
The 106 provides support for the following configurations of 60x processors and L2 cache:
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct–mapped, lookaside, L2 cache using the internal L2 cache controller of the 106
Up to four 60x processors plus an externally controlled L2 cache (such as the Motorola MPC2604GA integrated L2 lookaside
cache)
The memory interface controls processor and PCI interactions to main memory and is capable of supporting a variety of configura-
tions using DRAM, EDO, or SDRAM, and ROM or Flash ROM.
The PCI interface of the 106 complies with the
PCI Local Bus Specification,
Revision 2.1, and follows the guidelines in the
PCI
System Design Guide,
Revision 1.0, for host bridge architecture. The PCI interface connects the processor and memory buses to
the PCI bus, to which I/O components are connected. The PCI bus uses a 32–bit multiplexed address/data bus, plus various control
and error signals.
The PCI interface of the 106 functions as both a master and target device. As a master, the 106 supports read and write operations to
the PCI memory space, the PCI I/O space, and the PCI configuration space. The 106 also supports PCI special–cycle and interrupt–
acknowledge commands. As a target, the 106 supports read and write operations to system memory.
The 106 provides hardware support for four levels of power reduction—doze, nap, sleep, and suspend. The design of the TSPC106 is
fully static, allowing internal logic states to be preserved during all power saving modes.
4/40
TSPC106
2. PIN ASSIGNMENTS
2.1. CBGA303 package
Figure 2 contains the pin assignments for the TSPC106. Figure 3 provides a key to the shading in Figure 2.
16
W
V
DL26
DL24
MA1/
SDBA0/
AR9
MA2/
SDMA2/
AR10
MA3/
SDMA3/
AR11
MA5/
SDMA5/
AR13
MA6/
SDMA6/
AR14
MA8/
SDMA8/
AR16
15
DL28
DL27
14
DL30
DL29
13
DH31
DL31
12
DH29
DH30
11
DH27
DH28
10
DH25
DH26
9
DH23
DH24
8
DH21
DH20
7
DH19
DH18
6
DH17
DH16
5
DH15
DH14
DOE
/
DBGL2
4
DH13
DH12
3
DH11
DH10
2
DH9
DH8
1
DH7
DL22
W
V
U
DL23
DL25
DL14
PLL2
PLL0
DL12
DL10
DL4
DL2
DL0
DBG1
DH6
DL21
DL20
U
T
WE
DH0
DL15
PLL3
PLL1
DL13
DL11
DL3
DL1
TV/
BR2
BA0/
BR3
TWE
/
BG2
HIT
DIRTY_OU
T/
BG1
DIRTY IN/
BR1
ADS
/
DALE/
BRL2
DWE0
/
DBG2
DL19
DCS/
BG3
T
R
RCS0
MA4/
SDMA4/
AR12
MA0/
SDBA1/
SDMA0/
AR0
MA7/
SDMA7/
AR15
MA9/
SDMA9/
AR17
DH2
DH1
DL16
Vss
Vdd
DL9
DL5
Vss
Vdd
A0
TS
R
BA1/
DH4
DH3
Vss
Vdd
Vss
DL8
DL6
Vdd
Vss
Vdd
BAA
BGL2
P
A1
XATS/SDM
A1
P
N
DL17
DH5
Vdd
Vss
Vdd
DL7
DH22
Vss
Vdd
Vss
LBCLAIM
CI
A2
TA
N
M
RAS0/
CS0
DL18
Vss
Vdd
Vss
NC
NC
Vdd
Vss
Vdd
WT
GBL
A3
TT4
M
L
RRST
QACK
RAS1/
CS1
Vdd
CKO/
DWE2
RAS5/
CS5
Vss
Vdd
Vss
SYSCLK
DBG0
TBST
BR0
A4
TT3
L
K
MA10/
MA11/
SDMA11/ SDMA10/
AR18
AR19
MA12/
SDMA12/
AR20
QREQ
CAS2/
DQM2
BCTL0
CAS3/
DQM3
CAS0/
DQM0
RAS3/
CS3
RAS2/
CS2
RAS4/
CS4
RAS7/
CS7
Vdd
AVdd
Vss
Vdd
A9
A8
A7
BG0
A5
TT2
K
J
PPEN
RCS1
RAS6/
CS6
MCP
DBGLB/
CKE
PIRQ/
SDRAS
Vdd
Vss
Vss
Vdd
Vss
A11
A6
A13
A12
A10
TEA
J
H
G
F
CAS1/
DQM1
RTC
BCTL1
SUSPEND
CAS4/
DQM4
CAS6/
DQM6
CAS7/
DQM7
TRST
CAS5/
DQM5
TCK
Vss
Vdd
Vss
DWE1/
DBG3
LSSD_
MODE
Vdd
NC
PAR
PERR
NC
LOCK
DEVSEC
Vdd
Vss
Vdd
Vss
Vdd
Vss
Vdd
Vss
Vdd
A15
TSIZ1
A21
A14
TSIZ0
TSIZ2
A16
A17
ARTRY
TT1
TT0
A18
H
G
F
E
NMI
PAR1/
AR2
PAR3/
AR4
PAR7/
AR8
GNT
MDLE/SDC
AS
FOE
TDO
Vss
Vdd
SERR
IRDY
Vss
Vdd
A31
A29
A22
A20
A19
E
D
C
PAR0/
AR1
PAR2/
AR3
PAR4/
AR5
PAR6/
AR7
16
TMS
PAR5/
AR6
AD1
AD28
AD26
AD24
AD23
AD21
AD19
AD17
C/BE2
AD14
C/BE1
AD10
AD12
C/BE0
AD4
AD6
AD0
AD2
A30
A27
ISA_MASTE
R
/BERR
FLSHREQ
AACK
A23
A24
D
C
AD30
AD8
A25
B
TDI
AD7
AD11
AD15
TRDY
AD18
AD22
AD25
AD29
REQ
A28
A26
B
A
AD3
14
AD5
13
AD9
12
AD13
11
FRAME
STOP
AD16
8
AD20
7
C/BE3
AD27
5
AD31
4
MEMACK
A
1
15
10
9
6
3
2
Figure 2 : . Pin Assignments
NC
Vss
No Connect
Power Supply Ground
Vdd
AVdd
Power Supply Positive
Clock Power Supply Positive (K9)
Signals
VIEW
Figure 3 : Pin Assignments Shading Key
5/40
DSP 与 ARM 处理器
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