NTE8542
Integrated Circuit
Tri−State Quad I/O Register
General Description:
The NTE8542 is a 4−bit storage register with two terminals per bit which may be used as either inputs
or outputs when tied to two bus lines. Storage capability is obtained with positive edge triggered flip−
flops having common clock and asynchronous clear. Each I/O terminal can be forced to a high imped-
ance state (Hi−z state) using the Output Disable controls.
Features:
D
Series 54/74 compatible
D
Input clamp diodes
D
Propagation delays . . . . . . . 25ns
D
Power dissipation . . . . . . 400mW
D
Operation . . . . . . . . . . . . . 40MHz
Absolute Maximum Ratings:
(Note 1)
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Input Voltage, V
i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Output Voltage, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65°C
to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Recommended Operating Conditions:
Parameter
Supply Voltage
Temperature
Symbol
V
CC
T
A
Min
4.75
0
Max
5.25
+70
Unit
V
°C
Note 1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot
be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that
the devices should be operated at these limits. The table of “Electrical Characteristics” pro-
vides conditions for actual device operation.
Electrical Characteristics:
(Notes 2 and 3)
Parameter
Logical “1” Input Voltage
Logical “1” Input Current
Logical “0” Input Voltage
Logical “0” Input Current
Input Clamp Voltage
Logical “1” Output Voltage
Output Short Circuit Current
Logical “0” Output Voltage
Supply Current
TRI−STATE I/O Current with
Inputs and Outputs Disabled
Propagation Delay to a Logical “0”
from Clock to Output
Propagation Delay to a Logical “0”
from Clear to Output
Propagation Delay to a Logical “1”
from Clock to Output
Delay from Disable to High
Impedance State
(from Logical “1” Level)
Delay from Disable to High
Impedance State
(from Logical “0” Level)
Delay from Disable to Logical
“1” Level
(from High Impedance State)
Delay from Disable to Logical
“0” Level
(from High Impedance State)
Maximum Clock Frequency
Enable to Clock Set−Up Time
Enable to Clock Set−Up Time
t
pd0
t
pd0
t
pd1
t
1H
Symbol
V
IH
I
IH
V
IL
I
IL
V
CD
V
OH
I
OS
V
OL
I
CC
Test Conditions
V
CC
= Min
V
CC
= Max, V
IN
= 2.4V
V
CC
= Max, V
IN
= 5.5V
V
CC
= Min
V
CC
= Max, V
IN
= 0.4V
V
CC
= Min, I
IN
=
−12mA
V
CC
= Min, I
OUT
=
−800μ
V
CC
= Max, V
OUT
= 0V,
Note 4
V
CC
= Min, I
OUT
= 16mA
V
CC
= Max
V
CC
= Max, V
IN
= 2.4V
V
CC
= Max, V
IN
= 0.4V
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 5.0pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 5.0pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
Min
2.0
−
−
−
−
−
2.4
−25
−
−
−
−
−
−
−
−
Typ Max Unit
−
−
−
−
−
−
−
−
−
−
−
23
24
25
6.0
−
40
1.0
0.8
−1.5
−
−70
0.4
120
40
−40
35
36
38
15
V
μA
V
V
V
mA
V
mA
μA
ns
ns
ns
ns
−1.0 −1.6
mA
t
0H
−
15
25
ns
t
H1
−
20
30
ns
t
H0
−
17
25
ns
f
MAX
t
SO
t
SI
30
20
20
40
13
12
−
−
−
MHz
ns
ns
Electrical Characteristics (Cont’d):
(Notes 2 and 3)
Parameter
Date to Clock Set−Up Time
Date to Clock Set−Up Time
Data to Clock Hold Time
Data to Clock Hold Time
Minimum Clock Pulse Width
Minimum Clear Pulse Width
Symbol
t
SO
t
SI
t
HO
t
HI
PW
MIN
PW
MIN
Test Conditions
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
R
L
= 400Ω, C
L
= 50pF
T
A
= 25°C
Min
10
5.0
10
5.0
20
20
Typ Max Unit
4.5
−4.0
4.5
−3.5
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
Note 2. Unless otherwise specified min/max limits apply across the 0°C to +70°C range for the
NTE8542. All typicals are given for V
CC
= 5.0V and T
A
= 25°C.
Note 3. All currents into device pins shown as positive, out of device pins as negative, all voltages
referenced to GND unless otherwise noted. All values shown as max or min on absolute
value basis.
MODE OF OPERATION:
CLEAR
0
0
0
0
0
0
0
DIS
1
0
1
0
1
X
X
X
DIS
2
1
0
0
1
X
X
X
E
1
1
1
1
1
0
1
0
E
2
1
1
1
1
1
0
0
A
1
−
4
Q
Hi−z
Q
Hi−z
Data
Q
N
Data
B
1
−
4
Hi−z
Q
Q
Hi−z
Q
N
Data
Data
Comments
Output Data to Bus A
Output Data to Bus B
Output Data to Both Buses
Store Data With Outputs
in Hi−z State
Enter Data From Bus A
Enter Data From Bus B
Enter Data From Both
Buses (Logic “1” on Either
Will Dominate)
Clear
1
X
X
X
X
X
X
X = Don’t Care State
Q
N
= Data After Clock Transition
Pin Connection Diagram
DIS
2
A1
B1
B2
A2
E2
E1
GND
1
2
3
4
5
6
7
8
16
V
CC
15
DIS
1
14
A4
13
B4
12
B3
11
A3
10
Clock
9
Clear
16
9
1
8
.870 (22.0)
Max
.260
(6.6)
Max
.200 (5.08)
Max
.100 (2.54)
.700 (17.78)
.099 (2.5) Min
Microchip MCU
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