MDT10P7212
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed and smaller size with the low power consumption
and high noise immunity. On chip memory includes 4K
words of ROM, and 192 bytes of static RAM.
-8 analog inputs multiplexed into one A/D
converter
-10-bit resolution
TMR0: 8-bit real time clock/counter
TMR1: 16-bit real time clock/count
TMR2: 8-bit clock/counter (internal)
5 types of oscillator can be selected by
programming option:
2. Features
The followings are some of the features on the
hardware and software:
Fully CMOS static design
8-bit data bus
On chip EPROM size: 4.0 K words
Internal RAM size: 192 bytes
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage: 2.5 V ~ 5.5 V (PRD Disable)
4.5 V ~ 5.5 V (PRD Enable)
Operating frequency: DC ~ 20 MHz
The most fast execution time is 200 ns under 20
MHz in all single cycle instructions except the
branch instruction
Addressing modes include direct, indirect and
relative addressing modes
Power-on Reset
Power edge-detector Reset
Power range-detector Reset
Sleep Mode for power saving
Capture, Compare, PWM module
7 interrupt sources:
-External INT pin
-TMR0 timer, TMR1 timer, TMR2 timer
-A/D conversion completion
-Port B<7:4> interrupt on change
-CCP1
A/D converter module:
RC－Low cost RC oscillator
LFXT－Low frequency crystal oscillator
XTAL－Standard crystal oscillator
HFXT－High frequency crystal oscillator
IRC－Internal 8MHz RC oscillator
On-chip RC oscillator based Watchdog Timer
(WDT)
18/20 I/O pins with their own independent direction
control
3. Applications
The application areas of this MDT10P7212 range from
appliance motor control and high speed auto-motive to
low
power
remote
transmitters/receivers,
pointing
devices, and telecommunications processors, such as
Remote controller, small instruments, chargers, toy,
automobile and PC peripheral … etc.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 1
2007/11 VER1.2
MDT10P7212
4. Pin Assignment
PE2/AIC7 1
PA0/AIC0 2
PA1/AIC1 3
PA2/AIC2 4
PA3/AIC3 5
PA5/AIC4 6
PA4/T0CKI/VPP 7
VSS 8
PB0 9
PB1 10
PB2 11
PB3 12
24
23
22
21
20
19
18
17
16
15
14
13
PE1/AIC6
PE0/AIC5
PC2/CCP1
PC1/T1OSC1
PC0/T1OSC2
PC4
PC3
VDD
PB7
PB6
PB5
PB4
PE2/AIC7 1
PA0/AIC0 2
PA1/AIC1 3
PA2/AIC2 4
PA3/AIC3 5
PA5/AIC4 6
PA4/T0CKI/VPP 7
VSS 8
PB0 9
PB1 10
PB2 11
PB3 12
24
23
22
21
20
19
18
17
16
15
14
13
PE1/AIC6
PE0/AIC5
PC2/CCP1
PC1/T1OSC1
PC0/T1OSC2
OSC1
OSC2
VDD
PB7
PB6
PB5
PB4
MDT10P7212K11 (SKINNY)
MDT10P7212S11 (SOP)
5. Order information
Device
ROM
(words)
MDT10P7212K11
MDT10P7212S11
MDT10P7212K12
MDT10P7212S12
4K
4K
4K
4K
RAM
(bytes)
192
192
192
192
22
22
20
20
I/O
A/D
(10 bits)
8-channel
8-channel
8-channel
8-channel
MDT10P7212K12 (SKINNY)
MDT10P7212S12 (SOP)
Timer
(8/16)
2/1
2/1
2/1
2/1
CCP
INRC
(8Mhz)
Package
1
1
1
1
Yes
Yes
No
No
SKINNY
SOP
SKINNY
SOP
6. Pin Function Description
Pin Name
PA0~PA3, PA5
I/O
I/O
Function Description
Port A, TTL input level
Analog input channel
PA4/T0CKI/VPP
I/O
Real Time Clock/Counter, Schmitt Trigger input levels
Open drain output, Vpp input when programming
PB0~PB7
I/O
Port B, TTL input level/PB0: External interrupt input,
PB4~PB7: Interrupt on pin change
PC0~PC2
OSC1/PC4
I/O
I, I/O
Port C, Schmitt Trigger input levels
Oscillator Input/external clock input
PC4 in IRC mode
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 2
2007/11 VER1.2
MDT10P7212
Address
17
1E
1F
20~7F
BANK1
01
05
06
07
09
0C
0D
0E
12
1E
1F
A0~FF
TMR
CPIO A
CPIO B
CPIO C
CPIO E
PIEB1
PIEB2
PSTA
T2PER
ADRESL, The ADRESL register is not a writable register.
ADS1
General purpose register
CCP1CTL
ADRESH, The ADRESH register is not a writable register.
ADS0
General purpose register
Description
(1) IAR (Indirect Address Register): R00
(2) RTCC (Real Time Counter/Counter Register): R01
(3) PC (Program Counter): R02, R0A
Write PC --- from PCHLAT
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 4
2007/11 VER1.2
MDT10P7212
(4) STATUS (Status register): R03
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
/PF
/TF
RBS0
Carry bit
Half Carry bit
Zero bit
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit
0: 00h~7Fh (Bank0)
1: 80h~FFh (Bank1)
7-6
--
General purpose bit
Function
(5) MSR (Memory Bank Select Register): R04
Memory Bank Select Register:
0: 00h~7Fh (Bank0)
1: 80h~FFh (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A: R05
PA5~PA0, I/O Register
(7) PORT B: R06
PB7~PB0, I/O Register
(8) PORT C: R07
PC4~PC0, I/O Register
(9) PORT E: R09
PE2~PE0, I/O Register
(10) PCHLAT: R0A
(11) INTS (Interrupt Status Register): R0B
Bit
0
1
2
Symbol
RBIF
INTF
TIF
Function
PORT B change interrupt flag, Set when PB <7:4> inputs change
Set when INT interrupt occurs
Set when TMR0 overflows
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 5
2007/11 VER1.2
单片机
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