MDT10P712
1. General Description
This EPROM-Based 8-bit micro-controller uses a
fully static CMOS technology process to achieve
higher speed and smaller size with the low power
consumption and high noise immunity. On chip
memory includes 1K words of ROM, and 128
bytes of static RAM.
converter
-8-bit resolution
TMR0: 8-bit real time clock/counter
TMR1: 16-bit real time clock/counter
TMR2: 8-bit clock/counter
4 types of oscillator can be selected by
programming option:
RC－Low cost RC oscillator
LFXT－Low frequency crystal oscillator
XTAL－Standard crystal oscillator
HFXT－High frequency crystal oscillator
2. Features
The followings are some of the features on the
hardware and software:
On-chip RC oscillator based Watchdog
Fully CMOS static design
Timer (WDT)
8-bit data bus
13 I/O pins with their own independent
On chip EPROM size: 1.0 K words
direction control
Internal RAM size: 128 bytes
37 single word instructions
14-bit instructions
3. Applications
8-level stacks
The application areas of this MDT10P712
Operating voltage:2.5V~5.5V(PRD disable) range from appliance motor control and high
4.5V~5.5V(PRD enable) speed auto-motive to low power remote
Operating frequency: DC ~ 20 MHz
transmitters/receivers, pointing devices, and
The most fast execution time is 200 ns telecommunications processors, such as
under 20MHz in all single cycle Remote controller, small instruments, chargers,
instructions except the branch instruction
toy, automobile and PC peripheral … etc.
Addressing modes include direct, indirect
and relative addressing modes
Power-on Reset
Power edge-detector Reset
Power range-detector Reset
Sleep Mode for power saving
Capture, Compare, PWM module
7 interrupt sources:
-External INT pin
-TMR0 timer, TMR1 timer, TMR2 timer
-A/D conversion completion
-PortB<7:4> interrupt on change
-CCP
A/D converter module:
-4 analog inputs multiplexed into one A/D
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 1
Preliminary 2007/8
Ver1.0
MDT10P712
4. Pin Assignment
18-pin PDIP/SOP
PA2/AIC2 1
18 PA1/AIC1
PA3/AIC3/Vref
PA4/RTCC
/MCLR
VSS
PB0/INT
PB1/T1OSO/T1CKI
PB2/T1OSI
PB3/CCP
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
PA0/AIC0
OSC1
OSC2
VDD
PB7
PB6
PB5
PB4
20-pin SSOP
PA2/AIC2 1
20 PA1/AIC1
PA3/AIC3/Vref
PA4/RTCC
/MCLR
VSS
VSS
PB0/INT
PB1/T1OSO/T1CKI
PB2/T1OSI
PB3/CCP
2
3
4
5
6
7
8
9
10
19
18
17
16
15
14
13
12
11
PA0/AIC0
OSC1
OSC2
VDD
VDD
PB7
PB6
PB5
PB4
5. Pin Function Description
Pin Name
PA0~PA3
PA4/RTCC
PB0~PB7
/MCLR
OSC1/CLKIN
OSC2/CLKOUT
VDD
VSS
I/O
I/O
I/O
I/O
I
I
O
Function Description
Port A, TTL input level, Analog input channel.
Real Time Clock/Counter, Schmitt Trigger input level.
Open drain output.
Port B, TTL input level, PB0: External Interrupt input.
PB4~PB7: Interrupt on pin change.
Master Clear, Schmitt Trigger input level.
Oscillator Input, External clock input.
Oscillator Output, In RC mode, the CLKOUT pin has
1/4 frequency of CLKIN.
Power supply
Ground
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 2
Preliminary 2007/8
Ver1.0
MDT10P712
6. Memory Map
(A) Register Map
Address
BANK0
00
01
02
03
04
05
06
07
0A
0B
0C
0E
0F
10
11
12
15
16
17
1E
1F
20~7F
BANK1
81
85
86
87
8C
8E
TMR
CPIO A
CPIO B
CPIOCCP
PIEB1
PSTA
Indirect Addressing Register
RTCC
PCL
STATUS
MSR
Port A
Port B
DATACCP
PCHLAT
INTS
PIFB1
TMR1L
TMR1H
T1STA
TMR2
T2STA
CCPL
CCPH
CCPCTL
ADRES
ADS0
General purpose register
Description
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 3
Preliminary 2007/8
Ver1.0
MDT10P712
Address
92
9F
A0~BF
T2PER
ADS1
General purpose register
Description
(1) IAR (Indirect Address Register): R00
(2) RTCC (Real Time Counter/Counter Register): R01
(3) PC (Program Counter): R02, R0A
Write PC --- from PCHLAT
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A12~A11
A10~A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register): R03
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
TF
RBS0
Carry bit
Half Carry bit
Zero bit
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit:
0: 00H --- 7FH (Bank0)
1: 80H --- FFH (Bank1)
7-6
——
General purpose bit
Function
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 4
Preliminary 2007/8
Ver1.0
MDT10P712
(5) MSR (Memory Bank Select Register): R04
Memory Bank Select Register:
0: 00~7F (Bank0)
1: 80~FF (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A: R05
PA4~PA0, I/O Register
(7) PORT B: R06
PB7~PB0, I/O Register
(8) DATACCP: R07
Bit
0
1
2
7~3
Symbol
DT1CK
--
DCCP
--
Unimplemented
CCP1 PIN. Controlled from software.
Unimplemented
Function
T1CKI PIN. Controlled from software.
(9) PCHLAT: R0A
(10) INTS (Interrupt Status Register): R0B
Bit
0
1
2
3
4
5
6
7
Symbol
RBIF
INTF
TIF
RBIE
INTS
TIS
PEIE
GIS
Function
PORTB<7~4> pin change interrupt flag.
Set when INT interrupt occurs. INT interrupt flag.
Set when TMR0 overflows.
0: disable PB change interrupt.
1: enable PB change interrupt.
0: disable INT interrupt.
1: enable INT interrupt.
0: disable TMR0 interrupt.
1: enable TMR0 interrupt.
0: disable all peripheral interrupt.
1: enable all peripheral interrupt.
0: disable global interrupt.
1: enable global interrupt.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 5
Preliminary 2007/8
Ver1.0
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
