MDT10F630
1. General Description
This 8-bit Micro-controller uses a fully static
CMOS technology to achieve high speed, small
size, low power and high noise immunity.
On chip memory includes 1 K words of Flash
ROM, and 128 bytes of EEPROM, and 64 bytes
of static RAM.
automotive
to
low
power
remote
and
toy,
transmitters/receivers,
controller,
small
pointing
devices,
chargers,
telecommunications processors, such as Remote
instruments,
automobile and PC peripheral … etc.
4. Pin Assignment
2. Features
Fully CMOS static design
8-bit data bus
On chip flash ROM size :
MDT10F630 -- 1 K words
Internal RAM size :
MDT10F630 -- 64 bytes
(64 general purpose registers)
128 bytes of EEPROM
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.3V ~ 5.5 V
Watchdog timer with on-chip RC oscillator
Interrupt capability
Timer0 : 8-bit timer with 3-bit prescaler
Timer1 : 16-bit timer with 2-bit prescaler
One analog comparator module
Sleep mode for power saving
PA with port change wake-up interrupt
Power-on Reset
12 I/O pins with their own independent
direction control
MDT10F630P11 (DIP)
MDT10F630S11 (SOP)
Vdd
OSC1/PA5
OSC2/PA4
PA3
PC5
PC4
PC3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vss
PA0/CIN+
PA1/CIN-
PA2/INT
PC0
PC1
PC2
MDT10F630P13 (DIP)
MDT10F630S13 (SOP)
Vdd
OSC1/PA5
OSC2/PA4
/MCLR
PC5
PC4
PC3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Vss
PA0/CIN+
PA1/CIN-
PA2/INT
PC0
PC1
PC2
3. Applications
The application areas of this MDT10F630 range
from appliance motor control and high speed
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.1
2008/4
Ver. 1.0
MDT10F630
5. Order Information
ROM
(Words)
1.0K
1.0K
1.0K
1.0K
RAM EEPROM
(Bytes) (Bytes)
64
64
64
64
128
128
128
128
Timer
Package
(8/16 bit)
1/1
1/1
1/1
1/1
14-DIP
14-DIP
14-SOP
14-SOP
Device
MDT10F630P11
MDT10F630P13
MDT10F630S11
MDT10F630S13
I/O
12
11
12
11
Comparators
1
1
1
1
Remark
Pin 4 is PA3
function
Pin 4 is /MCLR
external reset
function
Pin 4 is PA3
function
Pin 4 is /MCLR
external reset
function
6. Block Diagram
EEPROM
128×8
Stack Eight
Levels
8 bits
Flash ROM
1024 ×14
10 bits
Comparator
RAM
64 ×8
PA3
14 bits
Program
Counters
Instruction
Register
Special
Register
Port A
PA0~PA2
PA4~PA5
5 bits
Port C
Instruction
Decoder
Data
8bit
PC0~PC5
6 bits
Oscillator
circuit
Control
Circuit
D0~D7
TMR0
8 Bits
TMR1
16 Bits
Power on Reset
Power Down Reset
Watchdog Timer
Working Register
ALU
Status Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.2
2008/4
Ver. 1.0
MDT10F630
7. Pin Function Description
Pin Name
PA0/CIN+
I/O
I/O
Function Description
Port A, TTL input level, with program pull_hi and interrupt on pin change.
Comparator input.
PA1/CIN-
I/O
Port A, TTL input level, with program pull_hi and interrupt on pin change.
Comparator input.
PA2/T0CK/INT/COUT
I/O
Port A, TTL input level, with program pull_hi and interrupt on pin change.
Timer0 clock input.
External interrupt.
Comparator output.
PA3/MCLR
I
Port A, TTL input level, with program interrupt on pin change.
Master clear. Schmitt Trigger input level.
PA4/OSC2/T1G
I/O
Port A, TTL input level, with program pull_hi and interrupt on pin change.
Oscillator crystal output, in RC mode clock output Fosc/4 frequency.
Timer1 gate.
PA5/OSC1/T1CKI
I/O
Port A, TTL input level, with program pull_hi and interrupt on pin change.
Oscillator crystal input/external clock source input.
Timer1 clock input.
PC0 ~ 5
Vdd
Vss
I/O
Port C, TTL input level.
Power supply
Ground
8. Memory Map
8.1 Program memory :
0000H
0001H ~0003H
0004H
0005H
Peripheral interrupt Vector
Reset Vector
Program memory
03FFH
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.3
2008/4
Ver. 1.0
MDT10F630
8.2
Register file map :
Address
BANK 0
00
01
02
03
04
05
06
07
08~09
0A
0B
0C
0D
0E
0F
10
11~14
15
16
17~18
19
1A
1B
1C
1D
1E~1F
64
20~5F
General
Register
60~7F
Unimplemented memory location.
Mapped
in
Bank 0
E0~FF
A0~DF
CMSTA
VRSTA
EEDATA
EEADR
EECON1
EECON2
PAPHR
PAINTR
TMR1L
TMR1H
T1STA
INOSCR
PSTA
PCHLAT
INTS
PIFB1
PCHLAT
INTS
PIEB1
PORT C
CPIO C
IAR
RTCC
PCL
STATUS
MSR
PORT A
IAR
TMR
PCL
STATUS
MSR
CPIO A
Description
Address
BANK 1
80
81
82
83
84
85
86
87
88~89
8A
8B
8C
8D
8E
8F
90
91~94
95
96
97~98
99
9A
9B
9C
9D
9E~9F
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.4
2008/4
Ver. 1.0
MDT10F630
(1). 00H or 80H : IAR ( Indirect Address Register)
Use contents of MSR to address data memory (not a physical register)
(2). 01H : RTCC (Timer0 Counter)
8-bit real time clock/counter
(3). 02H or 82H : PCL (Program Counter Low Byte)
Low order 8 bits of the Program Counter (PC)
(4). 03H or 83H : STATUS (Status register)
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
/PF
/TF
page
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
WDT time-out Flag bit
Register page select bit :
0 : 00H --- 7FH
1 : 80H --- FFH
6—7
——
General purpose bit
Function
(5). 04H or 84H : MSR (Memory Select Register)
Memory Bank Select Register :
0 : 00~7F (Bank0)
1 : 80~FF (Bank1)
MSR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indirect Addressing Mode
(6). 05H : Port A data output register
Bit 7
Port A
-
Bit 6
-
Bit 5
PA5
Bit 4
PA4
Bit 3
PA3
Bit 2
PA2
Bit 1
PA1
Bit 0
PA0
Bit 7-6 : Unimplemented
Bit 5-0 : PA5~PA0, I/O Register
(7). 06H : Unimplemented Register.
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.5
2008/4
Ver. 1.0
嵌入式系统
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