4, 8 MEG x 72
NONBUFFERED DRAM DIMMs
DRAM
MODULE
FEATURES
• JEDEC-standard ECC pinout in a 168-pin, dual in-line
memory module (DIMM)
• 32MB (4 Meg x 72) and 64MB (8 Meg x 72)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All inputs, outputs and clocks are LVTTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Serial presence-detect (SPD)
MT6LDT472A (X),
MT12LDT872A (X)
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
OPTIONS
• Package
168-pin DIMM (gold)
• Timing
50ns access
60ns access
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
* EDO version only
MARKING
G
-5*
-6
None
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
FPM Operating Mode
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
60ns
35ns
30ns
15ns
40ns
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE0#
CAS0#
CAS1#
RAS0#
OE0#
V
SS
A0
A2
A4
A6
A8
A10
NC (A12)
V
DD
V
DD
RFU
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
V
SS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
RFU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
RFU
CAS4#
CAS5#
RAS1#
RFU
V
SS
A1
A3
A5
A7
A9
A11
NC (A13)
V
DD
RFU
RFU
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
RFU
RAS3#
CAS6#
CAS7#
RFU
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
RFU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
DD
NOTE:
Pin symbols in parentheses are not used on these modules but may be
used for other modules in this product family. They are for reference only.
4, 8 Meg x 72 Nonbuffered DRAM DIMMs
DM87.p65 – Rev. 10/98
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
4, 8 MEG x 72
NONBUFFERED DRAM DIMMs
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT6LDT472AG-5 X
MT6LDT472AG-6 X
MT12LDT872AG-5 X
MT12LDT872AG-6 X
CONFIGURATION
4 Meg x 72 ECC
4 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
SPEED
50ns
60ns
50ns
60ns
FPM Operating Mode
PART NUMBER
MT6LDT472AG-6
MT12LDT872AG-6
CONFIGURATION
4 Meg x 72 ECC
8 Meg x 72 ECC
SPEED
60ns
60ns
GENERAL DESCRIPTION
The MT6LDT472A (X) and MT12LDT872A (X) are ran-
domly accessed 32MB and 64MB memories organized in a
x72 configuration. They are specially processed to operate
from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits. Two copies of address
0 (A0 and B0) are defined to allow maximum performance
for four-byte applications which interleave between two
four-byte banks. A0 is common to the DRAMs used for
DQ0-DQ35, while B0 is common to the DRAMs used for
DQ36-DQ71. RAS# is used to latch the first 12 bits and CAS#
the latter 10 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data-
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
for CAS# precharge time (
t
CP) to occur without the output
data going invalid. This elimination of CAS# output control
provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also tristate the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 16 [MT4LC4M16R6]
DRAM data sheet for additional information on EDO
functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is pre-
served by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-
ONLY, CBR or HIDDEN) so that all combinations of RAS#
addresses (A0-A10/A11) are executed at least every
t
REF,
regardless of sequence. The CBR REFRESH cycle will in-
voke the internal refresh counter for automatic RAS#
addressing.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide 8 unique DIMM/
EEPROM addresses.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-MODE
cycle. The primary advantage of EDO is the availability of
data-out even after CAS# goes back HIGH. EDO provides
4, 8 Meg x 72 Nonbuffered DRAM DIMMs
DM87.p65 – Rev. 10/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
4, 8 MEG x 72
NONBUFFERED DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition, which
is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
SPD STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).
The SPD device will always respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.
SCL
SCL
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
SDA
START
BIT
STOP
BIT
Figure 1
DATA VALIDITY
Figure 2
DEFINITION OF START AND STOP
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
ACKNOWLEDGE RESPONSE FROM RECEIVER
4, 8 Meg x 72 Nonbuffered DRAM DIMMs
DM87.p65 – Rev. 10/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
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