TECHNOLOGY, INC.
MT4LC4M4E8(L)
4 MEG x 4 DRAM
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• Low power, 1mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR)
HIDDEN; optional Extended
• 2,048-cycle (11 row-, 11 column-addresses)
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum V
IH
level)
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE, OPTIONAL
EXTENDED REFRESH
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
(DA-2)
V
CC
DQ1
DQ2
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
Vss
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
Vss
OPTIONS
• Timing
60ns access
70ns access
• Refresh Rate
Standard 32ns period
Extended Refresh 128ns period
• Packages
Plastic SOJ (300 mil)
MARKING
-6
-7
None
L
DJ
• Part Number Example: MT4LC4M4E8DJ-6
KEY TIMING PARAMETERS
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
12ns
12ns
GENERAL DESCRIPTION
The MT4LC4M4E8(L) is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The MT4LC4M4E8(L)
?
R
?
A
/
S is used to latch the
first 11 bits and
?
C
?
A
/
S the latter 11 bits. READ and WRITE
cycles are selected with the
?
W
/
E input. A logic HIGH on
?
W
/
E dictates READ mode while a logic LOW on
?
W
/
E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of
?
W
/
E or
?
C
?
A
/
S, whichever occurs last. If
?
W
/
E goes LOW prior to
?
C
?
A
/
S going LOW, the output pins
remain open (High- Z) until the next
?
C
?
A
/
S cycle, regardless
of
?
O
/
E.
A logic HIGH on
?
WE dictates READ mode while a logic
/
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
MT4LC4M4E8(L)
D24.pm5 – Rev. 12/95
data-in (D) is latched by the falling edge of W
/
E or
/
C
/
AS,
?
/
whichever occurs last. An EARLY WRITE occurs when
?
W
/
E is taken LOW prior to
/
C
/
A
/
S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when
?
W
/
E falls after
/
C
/
A
/
S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
O
/
E. During LATE WRITE or READ-MODIFY-WRITE cycles,
?
O
/
E must be taken HIGH to disable the data-outputs prior to
?
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping
?
O
/
E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by
?
W
/
E and
?
O
/
E.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address-
defined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by
?
R
?
A
/
S followed by a col-
umn-address strobed-in by C
?
A
/
S.
?
C
?
A
/
S may be toggled-in
?
by holding
?
R
?
A
/
S LOW and strobing-in different column-
addresses, thus executing faster memory cycles. Returning
?
R
?
A
/
S HIGH terminates the PAGE MODE of operation.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT4LC4M4E8(L)
4 MEG x 4 DRAM
EDO PAGE MODE
The MT4LC4M4E8(L) provides EDO PAGE MODE which
is an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?
C
?
A
/
S returns HIGH. EDO allows
?
C
?
A
/
S precharge time (
t
CP)
to occur without the output data going invalid. This elimi-
nation of C
?
AS output control allows pipeline READs.
? /
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
AS. EDO-PAGE-MODE DRAMs operate similarly to
/
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after
?
C
?
A
/
S goes HIGH during READs,
provided
?
R
?
AS and
?
O
/
E are held LOW. If
?
O
/
E is pulsed while
/
?
R
?
A
/
S and
?
C
?
A
/
S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If
?
OE is toggled or
/
pulsed after
?
C
?
A
/
S goes HIGH while
?
R
?
AS remains LOW,
/
data will transition to and remain High-Z (refer to Figure 1).
?
W
/
E can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
?
O
/
E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing
?
W
/
E to the idle banks during
?
C
?
A
/
S high time
will also High-Z the outputs. Independent of
?
O
/
E control,
the outputs will disable after
t
OFF, which is referenced
from the rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
RAS
V IH
V IL
CAS
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
t OD
t OES
VALID DATA (A)
VALID DATA (B)
t OD
t OEHC
VALID DATA (C)
t OD
VALID DATA (D)
OE
V IH
V IL
t OE
t OEP
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEP is met.
Figure 1
OUTPUT ENABLE AND DISABLE
MT4LC4M4E8(L)
D24.pm5 – Rev. 12/95
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT4LC4M4E8(L)
4 MEG x 4 DRAM
REFRESH
Preserve correct memory cell data by maintaining power
and executing a
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
AS refresh
/
cycle (?R
?
A
/
S ONLY, CBR, or HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
? ? /
32ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic
?
R
?
A
/
S addressing.
An optional extended refresh mode is also available on
the MT4LC4M4E8 L. The “L” version allows the user the
choice of a dynamic refresh mode at the extended refresh
period of 128ms, four times longer than the standard 32ms
specification.
RAS
V IH
V IL
CAS
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ V IOH
V IOL
OPEN
VALID DATA (A)
t WHZ
VALID DATA (B)
t WHZ
INPUT DATA (C)
WE
V IH
V IL
V IH
V IL
t WPZ
OE
The DQs go to High-Z if WE falls, and if
t
WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
?
W
/
E CONTROL OF DQs
MT4LC4M4E8(L)
D24.pm5 – Rev. 12/95
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT4LC4M4E8(L)
4 MEG x 4 DRAM
FUNCTIONAL BLOCK DIAGRAM
WE
CAS
DATA-IN
BUFFER
4
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
4
4
DQ1
DQ2
DQ3
DQ4
OE
COLUMN-
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
COMPLEMENT
SELECT
11
11
ROW-
ADDRESS
BUFFERS (11)
ROW
DECODER
ROW SELECT
(2 of 4096)
2048
2048
2048
2048
11
2048
4096 x 1024 x 4
MEMORY
ARRAY
RAS
NO. 1 CLOCK
GENERATOR
ROW TRANSFER
ROW TRANSFER
(1 OF 2)
(1 OF 2)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
10
1
COLUMN
DECODER
1024
4
SENSE AMPLIFIERS
I/O GATING
1024
REFRESH
COUNTER
V
DD
Vss
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
EDO-PAGE-MODE
READ
EDO-PAGE-MODE
EARLY-WRITE
EDO-PAGE-MODE
READ-WRITE
HIDDEN
REFRESH
?
R
?
A
/
S-ONLY REFRESH
CBR REFRESH
MT4LC4M4E8(L)
D24.pm5 – Rev. 12/95
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out
Data-Out, Data-In
Data-Out, Data-In
Data-Out
Data-In
High-Z
High-Z
?
R
?
A
/
S
H
L
L
L
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Any Cycle
1st Cycle
2nd Cycle
READ
WRITE
L
L
L
L
L
L
L
L>H>L
L>H>L
L
H>L
?
C
?
A
/
S
H>X
L
L
L
H>L
H>L
H>L
H>L
L>H
H>L
H>L
L
L
H
L
?
WE
/
X
H
L
H>L
H
H
L
L
H
H>L
H>L
H
L
X
H
?
O
/
E
X
L
X
L>H
L
L
X
X
L
L>H
L>H
L
X
X
X
t
R
t
C
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
n/a
ROW
n/a
ROW
ROW
ROW
X
X
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
COL
COL
n/a
X
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT4LC4M4E8(L)
4 MEG x 4 DRAM
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
pin Relative to V
SS
................. -1V to +4.6V
Voltage on NC, Inputs or I/O pins
Relative to V
SS
.................................................... -1V to +5.5V
Operating Temperature, T
A
(ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................. -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3) (V
CC
= +3.3V
±0.3V)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs (including NC pins)
Input Low (Logic 0) Voltage, all inputs (including NC pins)
INPUT LEAKAGE CURRENT
Any input 0V
≤
V
IN
≤
5.5V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V
≤
V
OUT
≤
5.5V)
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
SYMBOL
V
CC
V
IH
V
IL
I
I
I
OZ
V
OH
V
OL
MIN
3.0
2.0
-1.0
-2
-10
2.4
0.4
MAX
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(?R
?
A
/
S =
?
C
?
A
/
S = V
IH
)
STANDBY CURRENT: (CMOS)
(?R
?
AS =
?
C
?
AS = other inputs = V
CC
-0.2V)
/
/
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(?R
?
A
/
S,
?
C
?
A
/
S, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(?R
?
A
/
S = V
IL
,
?
C
?
A
/
S, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT:
?
R
?
A
/
S ONLY
Average power supply current
(?R
?
A
/
S cycling,
?
C
?
A
/
S = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(?R
?
A
/
S,
?
C
?
A
/
S, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended (L version only)
Average power supply current:
?
C
?
A
/
S = 0.2V or CBR cycling;
?
R
?
AS =
t
RAS (MIN);
?
W
/
E= Vcc -0.2V; A0-A10,
?
O
/
E and D
IN
= V
CC
-0.2V or
/
0.2V (D
IN
may be left open);
t
RC = 62.5µs (2,048 rows at 62.5µs = 128ms)
SYM
I
CC
1
-6
2
-7
2
500
150
UNITS
mA
µA
µA
NOTES
MAX
3.6
5.5
0.8
2
10
UNITS
V
V
V
µA
µA
V
V
4
NOTES
I
CC
2
500
I
CC
2
150
(L only)
I
CC
3
120
110
mA
5, 6
I
CC
4
110
100
mA
5, 6
I
CC
5
120
110
mA
5, 6
I
CC
6
120
110
mA
5, 7
I
CC
7
300
(L only)
300
µA
5, 7
MT4LC4M4E8(L)
D24.pm5 – Rev. 12/95
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
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