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TSB43AA82, TSB43AA82I
(iSphynx II)
1394 Integrated PHY and Link Layer Controller
for SBP 2 Products and DPP Products
Data Manual
April 2004
MSDS 1394
SLLS461F
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2004, Texas Instruments Incorporated
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www.ti.com/military
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www.ti.com/wireless
Contents
Section
1
Title
Page
1−1
1−1
1−2
1−3
1−4
1−4
1−5
1−5
1−6
1−7
1−7
1−8
1−8
1−9
2−1
2−2
2−2
2−2
2−2
2−2
2−2
2−3
2−3
2−3
2−3
2−3
2−3
2−4
2−4
2−5
3−1
3−1
3−1
3−6
3−6
3−6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1
DMA/Bulky Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2
Microcontroller/Microprocessor Signals . . . . . . . . . . . . . . . .
1.4.3
Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.4
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.5
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.6
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Assignments for TSB43AA82 . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
144-Terminal PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2
176-Terminal GGW Package . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Host I/F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
DMA I/F (Bulky Data I/F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Configuration Register (CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Fast ORB Exchanger (FOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Auto Response (AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Transaction/Timer Manager (TrMgr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Packet Distributor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Packetizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9
Configuration ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Link Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 PHY (and PHY Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 Example System Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13.1
Asynchronous Mode With Separate Microcontroller
and DMA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13.2
SCSI Mode With Shared Microcontroller and DMA Bus . .
Configuration Register (CFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Data Bit/Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Write/Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
CFR Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
Version/Revision Register at 00h . . . . . . . . . . . . . . . . . . . . .
2
3
iii
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
3.4.19
3.4.20
3.4.21
3.4.22
3.4.23
3.4.24
3.4.25
3.4.26
3.4.27
3.4.28
3.4.29
3.4.30
3.4.31
3.4.32
3.4.33
3.4.34
3.4.35
3.4.36
3.4.37
3.4.38
3.4.39
3.4.40
3.4.41
Miscellaneous Register at 04h . . . . . . . . . . . . . . . . . . . . . . . .
Control Register at 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt/Interrupt Mask Registers at 0Ch/10h . . . . . . . . . .
Cycle Timer Register at 14h . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics Register at 18h . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved at 1Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PHY Access Register at 20h . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Reset Register at 24h . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Limit Register at 28h . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATF Status Register at 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . .
ARF Status Register at 30h . . . . . . . . . . . . . . . . . . . . . . . . . .
MTQ Status Register at 34h . . . . . . . . . . . . . . . . . . . . . . . . . .
MRF Status Register at 38h . . . . . . . . . . . . . . . . . . . . . . . . . .
CTQ Status Register at 3Ch . . . . . . . . . . . . . . . . . . . . . . . . . .
CRF Status Register at 40h . . . . . . . . . . . . . . . . . . . . . . . . . .
ORB Fetch Control Register at 44h . . . . . . . . . . . . . . . . . . .
Management Agent Register at 48h . . . . . . . . . . . . . . . . . . .
Command Agent Register at 4Ch . . . . . . . . . . . . . . . . . . . . .
Agent Control Register at 50h . . . . . . . . . . . . . . . . . . . . . . . .
ORB Pointer Register 1 at 54h . . . . . . . . . . . . . . . . . . . . . . .
ORB Pointer Register 2 at 58h . . . . . . . . . . . . . . . . . . . . . . .
Agent Status Register at 5Ch . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Timer Control Register at 60h . . . . . . . . . . . . .
Transaction Timer Status Registers at 64h, 68h, 6Ch . . . .
Write-First, Write-Continue, and Write-Update Registers
at 70h, 74h, 78h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved at 7Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARF, MRF, and CRF Data Read Registers
at 80h, 84h, 88h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration ROM Control Register at 8Ch . . . . . . . . . . . .
DMA Control Register at 90h . . . . . . . . . . . . . . . . . . . . . . . . .
Bulky Interface Control Register at 94h . . . . . . . . . . . . . . . .
DTF/DRF and DTF/DRF Page Table Size Register
at 98h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTF/DRF Available Register at 9Ch . . . . . . . . . . . . . . . . . . .
DTF/DRF Acknowledge Register at A0h . . . . . . . . . . . . . . .
DTF First and Continue Register at A4h . . . . . . . . . . . . . . .
DTF Update Register at A8h . . . . . . . . . . . . . . . . . . . . . . . . .
DRF Data Read Register at ACh . . . . . . . . . . . . . . . . . . . . . .
DTF Control Registers at B0h, B4h, B8h, and BCh . . . . . .
DRF Control Registers at C0h, C4h, C8h, and CCh
(DRPktz at 90h = 0)—Direct . . . . . . . . . . . . . . . . . . . . . . . . .
DRF Control Registers at C0h, C4h, C8h, and CCh
(DRPktz at 90h = 1)—Packetizer . . . . . . . . . . . . . . . . . . . . .
DRF Header Registers at D0h, D4h, D8h, and DCh . . . . .
3−7
3−8
3−9
3−10
3−10
3−11
3−11
3−11
3−12
3−12
3−13
3−13
3−14
3−14
3−15
3−16
3−17
3−17
3−17
3−18
3−18
3−19
3−20
3−21
3−22
3−22
3−22
3−23
3−23
3−25
3−26
3−26
3−26
3−27
3−27
3−27
3−27
3−29
3−30
3−31
iv
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