MD7120
High Speed, 200V, Full H-Bridge MOSFET Driver
Features
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HVCMOS
®
technology for high performance
All N-MOSFET full-bridge driver
Designed for 200V bridge supply voltage
Up to 1.0MHz operation frequency
Greater than 90% efficiency
Designed for low total harmonic distortion
Single voltage drive power supply +12V
Smart logic voltage threshold
Resistor programmable OCP threshold
UVP function built-in
Accurate and adjustable dead time
32-Lead QFN package
General Description
The Supertex MD7120 is a high voltage, high speed, full-bridge driver.
It is ideal for Class-D audio amplifier applications and other high
frequency PWM driver applications, such as motor driving. This high-
voltage and high-speed driver can also be used for other applications:
as a piezo-electric transducer driver; as a MOSFET driver in a switched
mode power supply; or as a two channel driver for half-bridge power
stages.
The new IC topology is designed to drive dual N-MOSFETs as power
switches for both the high side and low side. It consists of controller
logic circuits, level translators, and a bootstrap floating powered gate
driver and over current protection circuits without using current sensing
resistors. The thresholds of the OCP for the high and low side are
resistor-programmable.
The power MOSFET top drain can be connected to up to +200V
while the bottom N-channel MOSFET source is grounded. They are
designed to provide 3.0A peak driving current with well-matched output
impendence and propagation delay on the high and low sides, as well
as from device-to-device.
The EN pin serves a dual purpose: the logic high level is used to
compute the threshold voltage level of inputs; and the logic low level
disables the outputs. The IC is in a low inductance and thermally
enhanced package.
Applications
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Class-D audio amplifier
High frequency PWM motor control
High frequency switching power supply
Ultrasound transducer drivers
High voltage waveform generator
Typical Application Circuit
AV
DD
V
DD1
+12V
R1
V
DD2
RP1
D1
BS1
D1
+200V
C1
M1
D3
Level
Translator
EN
INA
INB
OPF
GND
Driver
G1
GS1
R4
S1
L1
Level
Translator
V
DD
Driver
V
REF
G2
GS2
R5
M2
D4
+1.8 or 5.0V
Logic
Logic
UVP
OTP
OCP
S2
D1, D3
S1 - 4
GS1 - 4
+12V
D3
RP3
BS3
G3
GS3
S3
V
DD
R6
D2
R8
+200V
C3
CTV
Monitor
Level
Translator
Driver
C2
M3
D5
L2
C4
Level
Translator
V
SS
RDT
R3
RP2
Driver
G4
GS4
S4
R7
M4
D6
R2
MD7120
1
MD7120
Ordering Information
Package Option
Device
7x7mm body,
1.00mm height (max.),
0.65 pitch
32-Lead QFN,
MD7120
MD7120K6-G
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
32
1
Absolute Maximum Ratings
Parameter
V
DD
, (BS1-S1), (BS3-S3) supply voltage
V
PP
, high voltage supply
EN, IN
A
, IN
B
logic input voltage
OPF, open drain output voltage
Junction operating temperature range
Storage temperature
Thermal resistance (θ
JA
)*
Value
-0.5V to 15V
10V to +220V
-0.5V to 7.5V
-0.5V to 15V
-40°C to +125°C
-65°C to 150°C
29.3
O
C/W
32-Lead QFN (K6)
(top view)
Product Marking
MD7120K6
LLLLLLLLL
YYWW
AAA
CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
* 1oz, 4-layer, 4x3” PCB
32-Lead QFN (K6)
DD
DC Electrical Characteristics
(Over operating conditions, unless otherwise specified. V
Sym
V
DD
V
PP
V
EN
V
PT
V
NT
V
HY
I
DDQ
I
DDEN
I
DD
R
IN
C
IN
Sym
R
HSC
R
HSK
R
LSC
R
LSK
Parameter
Positive drive supply voltage
High supply voltage
EN input voltage range
Input positive threshold
Input negative threshold
Input threshold hysteresis
V
DD
quiescent current, EN=0
V
DD
average current
V
DD
average current at 500KHz
Input logic impedance to GND
Logic input capacitance
Parameter
Sourcing output resistance
Sinking output resistance
Sourcing output resistance
Sinking output resistance
Min
9.0
-
1.8
-
30
9.0
-
-
-
-
-
Min
-
-
-
-
Typ
12
150
-
-
-
-
140
6.0
57
250
5.0
Typ
5.0
5.0
5.0
5.0
Max
13
200
5.0
70
-
30
-
-
-
-
10
Max
-
-
-
-
Units
V
V
V
%
%
%
µA
mA
mA
kΩ
pF
Units
Ω
Ω
Ω
Ω
---
---
---
= 12V, V
PP
= 200V, T
A
= 25°C)
Conditions
Percent of V
EN
voltage
Percent of V
EN
voltage
Percent of V
EN
voltage
---
INA = INB = 0 (measured)
INA = INB = 500KHz 50%, G1~4 to
S1~4 with four 1000pF load capacitors
---
---
Conditions
I
DS
= 1.0A
I
DS
= 1.0A
I
DS
= 1.0A
I
DS
= 1.0A
Gate Driver Outputs
2
MD7120
Under Voltage and Over Current / Temperature Protection
Sym
V
OL_OPF
V
PULL_UP
I
OPF
V
UVT
V
UVH
I
RP1
, I
RP3
I
RP2
V
GS1-4
T
OTP
T
OTH
Parameter
OPF flag output low voltage
Open drain pull-up voltage
OPF sinking current limit
V
DD
rising threshold
V
DD
UV hysteresis
High-side current reference
Low-side current reference
Gate sense voltage threshold
Over-temperature threshold
Over-temperature hysteresis
Min
-
-
-
6.8
-
-
-
4.5
95
-
Typ
-
-
1.0
7.8
0.6
55
55
6.0
110
7.0
Max
1.0
15
1.5
8.8
-
-
-
7.5
120
-
(Over operating conditions, unless otherwise specified. V
DD
= 12V, V
PP
= 200V, T
A
= 0 to 70°C)
Units
V
V
mA
V
V
µA
µA
V
O
Conditions
OPF = low, I
PULL_UP
= 1.0mA
I
OPF
= 1.0mA
---
---
---
---
---
Reference to S1-4
If over temperature, OPF low and
M1~4 off
---
V
DD
= 12V, V
PP
= 200V, T
A
= 0 to 70°C)
C
C
O
AC Electrical Characteristics
(Over operating conditions, unless otherwise specified.
Sym
f
S
t
dr
t
df
t
r
t
f
t
dm
Δt
dtr
Δt
dta
THD
t
EN
t
PWR_UP
Parameter
Switch frequency
Switch on delay + dead time
Switch off delay time
Output rise time
Output fall time
Dead time matching
Dead time adjustable range
Dead time accuracy
Total Harmonic Distortion
Enable ready time
Power-up time
Min
-
-
-
-
-
-
15
-
-
-
-
Typ
-
35
40
28
29
-
-
±5.0
0.0007
-
-
Max
1.0
-
-
-
-
±5
50
±10
-
80
200
Units
MHz
ns
ns
ns
ns
ns
ns
%
%
ns
µs
Conditions
---
When t
dt
= min
See timing diagram
With 1.0nF load
With 1.0nF load
Channel to channel
RDT = 1.0kΩ to 200kΩ
15ns to 50ns
Time jitter contribution, f
J
= 10Hz,
f
S
= 500KHz, f
A
= 1.0KHz
See timing diagram
See timing diagram
Logic Table
Logic Input
EN
1
1
1
1
0
INA
0
0
1
1
X
INB
0
1
0
1
X
L
L
H
H
Hi-Z
Power MOSFET Output
A Bridge Output
B Bridge Output
L
H
L
H
Hi-Z
3
MD7120
OCP Threshold vs RP1, 2, 3
8
7.2
6.4
OCP Threshold (V)
Dead Time (ns)
Dead Time vs RDT
150
135
120
105
90
75
60
45
30
15
0
5.6
4.8
4
3.2
2.4
1.6
0.8
0
10
21
32
43
54 65 76
RP1,2,3 (K)
87
98 109 120
0
60 120 180 240 300 360 420 480 540 600
RDT (K)
Logic V
PT/NT
/ V
EN
Curve
V
PT/NT
V
PT
2.0
1.5
1.0
0.5
0
0
1.0
2.0
3.0
4.0
5.0
V
NT
0.6V
V
EN
Switch Timing Diagram
50%
50%
Adjustable Delay Time Diagram
INA or INB
tdr
tdf
50%
50%
G1 or G3
90%
90%
90%
tdt
tdt
50%
10%
10%
tr
tf
10%
50%
G1 or G3
G2 or G4
4
MD7120
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
GND
AVDD
INA
EN
INB
OPF
VSS
NC
RDT
S4
G4
GS4
VDD2
NC
S3
G3
GS3
BS3
D3
RP1
RP3
D1
BS1
GS1
G1
S1
NC
VDD1
GS2
G2
S2
RP2
Function
Logic signal ground.
Logic AVDD voltage supply (+12V). Not connected to VDD1 or VDD2 internally.
Input logic control of the half-bridge A output.
Chip power enable, EN = Hi chip enabled, EN = Lo disabled, EN resets the OPF flag latch.
Input logic control of the half-bridge B output.
Open drain output of over/under voltage, over current or temperature flag, Active = Low.
Return of voltage supply.
Not connected.
Dead time program resistor.
Low side MOSFET source.
Low side MOSFET gate.
Low side MOSFET gate voltage sense.
Positive voltage supply (+12V). May not connected to VDD1 internally.
Not connected.
High side MOSFET source.
High side MOSFET gate.
High side MOSFET gate voltage sense.
High side boost external capacitor.
High side MOSFET drain.
High side program resistor OCP threshold for MOSFET M1.
High side program resistor OCP threshold for MOSFET M3.
High side MOSFET drain.
High side boost external capacitor.
High side MOSFET gate voltage sense.
High side MOSFET gate.
High side MOSFET source.
Not connected.
Positive voltage supply (+12V). May not connected to VDD2 internally.
Low side MOSFET gate voltage sense.
Low side MOSFET gate.
Low side MOSFET source.
Low side program resistor OCP threshold for MOSFET M2 and M4.
Note:
The thermal pad must be connected to VSS externally.
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