hmp
Description
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
128K x 32 FLASH MODULE
PUMA 68F4001-15/17/20
Issue 4.1 : August 1997
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Features
• Access Times of 150,170 and 200ns.
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
• Industrial, Military or Military(High Rel) Grade.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power :
1320 mW (max)
• Standby Power : -L Part (
CMOS
)
6.6 mW (max)
• Page Write (128 Bytes) in 10ms typ.
• DATA Polling and Toggle bit indication of end of
write.
• Hardware and Software Data Protection.
• Endurance of 10
4
Erase/write Cycles and Data
Retention Time of 10 years.
The PUMA 68F4001 is a 4Mbit CMOS FLASH
memory module organised as 128K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 150, 170 and 200ns. The output
width is user configurable as 8 , 16 or 32 bits using
four Chip Selects (CS1~4). The plastic device is
screened to ensure high reliability.
Page write (128 Bytes) is performed in 10ms with
Toggle bit and DATA polling indication of cycle
completion. The device features both hardware
and software data protection and a low power
standby of 6.6mW. Write cycle endurance is
10,000 Erase/Write cycles with a data retention
time of 10 years.
Block Diagram
Pin Definition
GND
VCC
CS3
CS4
NC
WE
A0
A2
A3
A4
A6
A1
A5
9
D0
A0~A16
OE
WE
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC
D1
D2
D3
D4
128K x 8
FLASH
128K x 8
FLASH
128K x 8
FLASH
128K x 8
FLASH
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
PUMA 68F4001
VIEW
FROM
ABOVE
A8
A7
A10
A9
55
54
53
52
51
50
49
48
47
46
45
44
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
GND
NC
NC
CS1
A11
CS2
OE
NC
NC
A13
A14
A15
A12
A16
Pin Functions
A0~16
Address Inputs
CS1~4
Chip Select
WE
Write Enable
V
CC
Power (+5V)
D0~31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
NC
NC
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
T
OPR
T
STG
V
IN
V
OUT
-55 to +125
-65 to +150
-0.5 to +7.0
-0.5 to +7.0
°
C
°
C
V
V
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
min
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
V
CC
V
IL
V
IH
T
A
T
AI
T
AM
4.5
-0.3
2.0
0
-40
-55
typ
5.0
0.8
-
-
-
-
max
5.5
V
V
CC
+0.3
70
85
125
V
V
°
C
°
C (I Suffix)
°
C (M,
MB
Suffix)
DC Electrical Characteristics
(T
A
=-55°C to +125°C,V
CC
=5V ± 10%)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Symbol
I
LI1
32 bit I
LO
32 bit I
CC32
16 bit I
CC16
8 bit I
CC8
Test Condition
min
-
-
-
-
-
-
-
-
2.4
max
40
40
240
126
69
12
1.2
0.4
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
V
IN
= GND to V
CC
V
IN
= GND to V
CC
, CS
(1)
=V
IH
CS
(1)
=OE=V
IL
, WE=V
IH
, I
OUT
=0mA, ƒ=5MHz
As above
As above
CS
(1)
= V
IH
, I
I/O
= 0mA, Other Inputs = V
IH
CS
(1)
= V
CC
-0.3V, I
I/O
= 0mA, Other Inputs = V
CC
I
OL
= 2.1mA.
I
OH
= -400µA.
Standby Supply Current TTL levels I
SB1
CMOS levels I
SB2
Output Low Voltage
Output High Voltage
V
OL
V
OH
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
Capacitance
(T
A
=25°C,ƒ=1MHz)
Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
CS1-4
Other Inputs
Symbol
C
IN1
C
IN2
C
OUT
Test Condition
V
IN
=0V
V
IN
=0V
V
OUT
=0V
typ
-
-
-
max Unit
16
34
22
pF
pF
pF
2
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Chip Select High to High Z Output
Output Enable High to High Z Output
Output Hold from Address Change
Symnbol
t
RC
t
AA
t
CS
t
OE
t
HZ
t
OHZ
t
OH
-15
min max
150
-
-
0
0
0
0
-
150
150
70
50
50
-
-17
min max
170
-
-
0
0
0
0
-
170
170
80
50
55
-
-20
min max
200
-
-
0
0
0
0
-
200
200
80
50
60
-
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
(1)
(1)
Notes:(1) t
HZ
is specified from OE or CS 1-4 whichever occurs first (Cl=5 pf).
Write Cycle
Parameter
Write Cycle Time
Address Set-up Time
Address Hold Time
Output Enable Set-up Time
Output Enable Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width
Write Enable High Recovery
Data Set-up Time
Data Hold Time
Delay to Next Write
Byte Load Cycle
Symbol
t
WC
t
AS
t
AH
t
OES
t
OEH
t
CS
t
CH
t
WP
t
WPH
t
DS
t
DH
t
DW
t
BLC
min
-
0
80
0
0
0
0
100
100
50
10
10
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
max
10
-
-
-
-
-
-
-
-
-
-
-
150
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC
=5V±10%
Output Test Load
I/O Pin
645
Ω
1.76V
100pF
3
PUMA 68F4001-15/17/20
ISSUE 4.1 : AUGUST 1997
Read Cycle Timing Waveform
Address
Address Valid
t
RC
t
CS
CS
t
OE
t
OLZ
t
OHZ
OE
t
LZ
t
OH
HIGH z
t
HZ
Dout
Output
Valid
t
AA
Output
Valid
Software Protected Write Waveform
OE
CE
t
WP
t
DLC
WE
t
AS
t
AH
t
WPH
BYTE ADDRESS
A0~A6
05555
02AAA
05555
A7~A16
t
DS
t
DH
55
A0
PAGE ADDRESS
t
WC
Data
AA
Byte 0
Byte 126
Byte 127
Note: (1) A7 through A16 must specify the page address during each high to low transition of Write Enable (or Chip select).
(2) Output Enable must be high only when Write Enable and Chip Select are both low.
(3) All bytes that are not loaded within the sector being programmed will be erased to FF.
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