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SN75LVDS84, SN75LVDS85
FLATLINK™ TRANSMITTERS
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
D
D
D
D
D
D
D
D
D
D
D
D
D
21:3 Data Channel Compression at up to
163 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
21 Data Channels Plus Clock In
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant Data Inputs
ESD Protection Exceeds 6 kV
SN75LVDS84 Has Falling Clock-Edge
Triggered Inputs, SN75LVDS85 Has Rising
Clock-Edge-Triggered Inputs
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
Consumes Less Than 1 mW When Disabled
Wide Phase-Lock Input Frequency Range:
31 MHz to 68 MHz
No External Components Required for PLL
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
Improved Replacement for the DS90C561
DGG PACKAGE
(TOP VIEW)
D4
V
CC
D5
D6
GND
D7
D8
V
CC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
V
CC
D18
D19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV
CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D20
description
NC – Not Connected
The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as
the SN75LVDS82 or SN75LVDS86.
When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge
and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
AVAILABLE OPTIONS†
LATCHING CLOCK EDGE
FALLING
SN75LVDS84DGG
SN75LVDS84DGGR
RISING
SN75LVDS85DGG
SN75LVDS85DGGR
† The R suffix indicates taped and reeled packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1999, Texas Instruments Incorporated
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1
SN75LVDS84, SN75LVDS85
FLATLINK™ TRANSMITTERS
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
description (continued)
The SN75LVDS84 or SN75LVDS85 require no external components and little or no control. The data bus
appears the same at the input to the transmitter and output of the receiver with the data transmission transparent
to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input
to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal
clears all internal registers to a low level.
The SN75LVDS84 and SN75LVDS85 are characterized for operation over ambient free-air temperatures of
0
_
C to 70
_
C.
functional block diagram
Parallel-Load 7-Bit
Shift Register
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
A,B, ...G
SHIFT/LOAD
CLK
Y2P
Y2M
Y1P
Y1M
7
D0 – D6
Y0P
Y0M
7
D7 – D13
7
D14 – D20
Control Logic
SHTDN
7× Clock/PLL
7×CLK
CLKIN
CLK
CLKINH
CLKOUTP
CLKOUTM
SN75LVDS84 only
2
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SN75LVDS84, SN75LVDS85
FLATLINK™ TRANSMITTERS
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
D0
CLKIN
(’LVDS85)
CLKIN
(’LVDS84)
CLKOUT
Previous Cycle
Current Cycle
D3
D2
Y0
D0–1
D6
D5
D4
Y1
D7–1
D13
D12
D11
D10
D9
Y2
D14–1
D20
D19
D18
D17
D16
Figure 1. Load and Shift Timing Sequences
schematics of input and output
EQUIVALENT OF EACH INPUT
EQUIVALENT OF EACH OUTPUT
VCC
VCC
D or
SHTDN
50
Ω
5
Ω
10 kΩ
7V
300 kΩ
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ÎÎ
ÎÎ
ÎÎ
D1
D0
D8
D7
D15
D14
ÏÏ
ÏÏ
ÏÏ
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
ÎÎ
ÏÏ
ÏÏ
ÏÏ
ÏÏÏÏ
ÏÏÏÏ
Next
Cycle
D6+1
D13+1
D20+1
YnP or YnM
7V
3
SN75LVDS84, SN75LVDS85
FLATLINK™ TRANSMITTERS
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to 4 V
Output voltage range, V
O
(all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input voltage range, V
I
(all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65
_
C to 150
_
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
_
C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
DGG
TA
≤
25°C
POWER RATING
1316 mW
DERATING FACTOR‡
ABOVE TA = 25°C
13.1 mW/°C
TA = 70°C
POWER RATING
726 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.
recommended operating conditions
MIN
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Differential load impedance, ZL
Operating free-air temperature, TA
90
0
3
2
0.8
132
70
NOM
3.3
MAX
3.6
UNIT
V
V
V
Ω
°C
timing requirements
MIN
tc
tw
tt
tsu
th
Input clock period
Pulse duration, high-level input clock
Transition time, input signal
Setup time, data, D0 – D27 valid before CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2)
Hold time, data, D0 – D27 valid after CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2)
3
1.5
14.7
0.4 tc
NOM
MAX
32.4
0.6 tc
5
UNIT
ns
ns
ns
ns
ns
4
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