SL2101
Synthesized Broadband Converter with
Programmable Power
Data Sheet
Features
•
•
Single chip synthesized broadband solution
Configurable as both up converter and
downconverter requirements in double
conversion tuner applications
Incorporates 8 programmable mixer power
settings
Compatible with digital and analogue system
requirements
CSO -65 dBc, CTB -68 dBc (typical)
Extremely low phase noise balanced local
oscillator, with very low fundamental and
harmonic radiation
PLL frequency synthesizer designed for high
comparison frequencies and low phase noise
Buffered crystal output for pipelining system
reference frequency
I
2
C Controlled
Ordering Information
SL2101C/KG/NP1P
SL2101C/KG/NP1Q
SL2101C/KG/NP2P
SL2101C/KG/NP2Q
SL2101C/KG/LH2N
SL2101C/KG/LH2Q
SSOP
SSOP
SSOP*
SSOP*
MLP*
MLP*
Tubes
Tape & Reel
Tubes
Tape & Reel
Trays
Tape& Reel
August 2004
•
•
•
•
* Pb free
All codes baked and drypacked
-40°C to +85°C
•
•
•
Description
The SL2101 is a fully integrated single chip broadband
mixer oscillator with low phase noise PLL frequency
synthesizer. It is intended for use in double conversion
tuners as both the up and down converter and is
compatible with HIIF frequencies up to 1.4 GHz and all
standard tuner IF output frequencies. It also contains a
programmable power facility for use in systems where
power consumption is important.
The device contains all elements necessary, with the
exception of local oscillator tuning network, loop filter
and crystal reference to produce a complete
synthesized block converter, compatible with digital
and analogue requirements.
Applications
•
•
•
•
•
Double conversion tuners
Digital Terrestrial tuners
Cable telephony
Cable Modems
MATV
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
SL2101
Data Sheet
XTAL CAP
XTAL
SDA
SCL
BUFREF
Vccd
Vee
Vee
RF
RFB
Vee
VccRF
Vee
IFOUTPUTB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PUMP
DRIVE
PORT P0
Vee
ADD
Vee
VccLO
LOB
LO
VccLO
Vee
VccLO
Vee
IFOUTPUT
NP 28
Figure 2 - Pin Diagram SSOP Package
XTAL CAP
Vccd
nc
nc
RF
RFB
nc
VccRF
1
2
3
4
28 27 26 25 24 23 22
21
Pin 1 Ident
20
19
18
17
16
8
nc
9
nc
15
10 11 12 13 14
IFOUTPUTB
IFOUT
nc
nc
VccLO
PORT P0
DRIVE
PUMP
SDA
XTAL
SCL
ADD
nc
VccLO
LOB
LO
VccLO
nc
5
6
7
Vee to pad
under package
Figure 3 - Pin Diagram MLP Package
2
Zarlink Semiconductor Inc.
SL2101
Quick Reference Data
All data applies at maximum power setting with the following conditions unless otherwise stated;
a) nominal loads as follows;
1220 MHz output load as in Figure 4
44 MHz output load as in Figure 5
b) input signal per carrier of 63 dBµV
Characteristic
RF input operating range
Input noise figure, SSB,
50-860 MHz
860-1400
Conversion gain
CTB (fully loaded matrix)
CSO (fully loaded matrix)
P1 dB input referred
Local oscillator phase noise as upconverter
SSB @ 10 kHz offset
SSB @ 100 kHz offset
Local oscillator phase noise as downconverter
SSB @ 10 kHz offset
SSB @ 100 kHz offset
Local oscillator phase noise floor
PLL spurs on converted output with input @ 60 dBµV
PLL maximum comparison frequency
PLL phase noise at phase detector
*dBm assumes a 75
Ω
characteristic impedance, and 0 dBm = 109 dBµV
Data Sheet
Units
50-1400
6.5 - 8.5
8.5 - 12
12
-68
-65
110
-90
-112
-93
-115
-136
<-70
4
-152
MHz
dB
dB
dB
dBc
dBc
dBµV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
MHz
dBc/Hz
Functional Description
The SL2101 is a broadband wide dynamic range mixer oscillator with on-board I
2
C bus controlled PLL frequency
synthesizer, optimized for application in double conversion tuner systems as both the up and down converter. It
also has application in any system where a wide dynamic range broadband synthesized frequency converter is
required.
The SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in Figures 2
and 3 for the SSOP and MLP packages and the block diagram in Figure 1.
The device also contains a programmable facility to adjust the power in the lna/mixer so allowing power to be
traded against intermodulation performance for power critical applications, such as telephony modems.
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Zarlink Semiconductor Inc.
SL2101
Converter Section
Data Sheet
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to
the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region
of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite
distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the
mixer section and back isolation from the local oscillator section.
The lna/mixer current and hence signal handling and device power consumption are programmable through the I
2
C
bus as tabulated in Figure 7.
The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and
9 respectively and for narrow band downconversion in Figures 10 and 11 respectively. The input referred two tone
intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and
gain versus frequency and NF specification limits, over selectable power settings are contained in Figures 13, 14
and 15 respectively.
The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this
stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The
oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator
application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The
typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure
19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator.
Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of
an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner
output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example
with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is
shown in Figure 4, which will typically be terminated with a differential 200 load. When used as a narrowband
downconverter the output should be differentially loaded with a discrete differential to single ended converter as in
Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in
which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is
contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20.
The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22
respectively.
In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation
performance.
The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference
Data'.
PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference
frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source.
The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which
enables the generation of a loop with good phase noise performance.
The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The
programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits,
and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in figure
23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when
driving a second SL2101 as a downconverter.
The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop
filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the
oscillator.
The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to
port P0 by programming the device into test mode. The test modes are described in Figure 26.
The crystal reference frequency can be switched to BUFREF output by bit RE as described in Figure 27. The
BUFREF output is not available on the MLP package.
Programming
The SL2101 is controlled by an I
2
C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I
2
C bus format. The device can
either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into
write mode if it is low, and read mode if it is high. Tables 1 and 2 in Figure 28 illustrate the format of the data. The
device can be programmed to respond to several addresses, which enables the use of more than one device in an
I
2
C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input.
When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are received. When the device is programmed into read
mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to
read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write Mode
With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 2
14
-2
0
inclusive.
Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29.
Byte 5 controls the test modes, see Figure 26, the buffered crystal reference output select RE, see Figure 27, the
power setting, see Figure 7 and the output port P0.
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows
the same procedure, without re-addressing the device. This procedure continues until a STOP condition is
received. The STOP condition can be generated after any data byte, if however it occurs during a byte
transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP
condition.
Read Mode
When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped
below 3V (at 25° C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is
terminated by a STOP command. When POR is set high this indicates that the programmed information may have
been corrupted and the device reset to the power up condition.
Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
5
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