TH7818A
50 MHz 1024 Pixels Linear CCD
Datasheet
1. Features
•
•
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•
•
•
•
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Data Rate up to 50 MHz ( Two Outputs at 25 MHz Each)
Pixel Size: 14 µm x 14 µm (14 µm Pitch)
250 to 1100 nm Spectral Range
High Sensitivity and Lag-free Photodiodes
Low Noise
Antiblooming
Exposure Control
20 Pin 0.4" DIL Package
2. Applications
The TH7813 and TH7814 linear arrays are based on e2v’s know-how in terms of design and technology. Flexibility and per-
formance of these devices give the opportunity to use them in most vision systems for industrial applications (web
inspection, process control, sorting and inspection of various parts), document scanning metrology, etc.
Figure 2-1.
Block Diagram
VDD1
Odd Pixels CDD Shift Register
N-1
N-3
Storage Area
Photo Diode Area
Storage Area
Even Pixels CCD Shift Register
ΦL1
ΦL2
3
1
VDR
ΦR
VOS2
VOS1
VS
N N-1 N-2 N-3
N
N-2
4 3 2 1
4
2
ΦA
VA
ΦP
VST
VGS VDD2
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e2v semiconductors SAS 2008
0864B–IMAGE–03/08
TH7818A
3. Pin Identification
All pins must be connected.
Figure 3-1.
Package Top View
VDR VSS VOS2 VDD2 VSS
ΦR
ΦL1 ΦL2
VSS
ΦP
20
11
1
VSS VGS VOS1 VDD1 VS
VSS
VA
VST VSS
10
ΦA
Table 3-1.
Pin n°
4, 17
3, 18
5
20
2
14
13
15
10
7
8
11
Pin Description
Symbol
VDD1,2
VOS1,2
VS
VDR
VGS
ΦL1
ΦL2
ΦR
ΦA
VA
VST
ΦP
VSS
Readout register clocks
Reset clock
Antiblooming gate bias/clock
Antiblooming drain bias
Storage gate bias
Transfer gate clock
Ground, Optical shield grounding
(internally connected)
Function
Output amplifiers drain supply
Video outputs
Output amplifiers substrate bias
Reset drain supply
Output gate bias
1, 6, 9, 12, 16, 19
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TH7818A
4. Absolute Maximum Ratings
Table 4-1.
Absolute Maximum Ratings
(*NOTICE:)
*NOTICE:
Stresses above those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent
device failure. Functionally at or above these lim-
its is not implied. Exposure to absolute maximum
ratings for extended periods may affect device
reliability.
Storage temperature...................................... -55°C to +150°C
Operating temperature..................................... -40°C to +85°C
Thermal cycling ..........................................................15°C/mn
Maximum applied voltages:
2, 8, 10, 11, 13, 14, 15............................................ -0.3 to 15V
4, 5, 7, 17, 20.......................................................... -0.3 to 16V
1, 6, 9, 12, 16, 19...................................................0V (ground)
5. Operating Range and Operating Precautions
Operating range defines the limits between which the functioning is guaranteed. Electrical limits of
applied signals are given in
Section 6.
Shorting the video outputs to any other pin, even temporarily, can permanently damage the on-chip out-
put amplifier.
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TH7818A
6. Operating Conditions
Table 6-1.
DC Characteristics
Value
Parameter
Output amplifier drain supply
Storage gate bias
Reset bias
Antiblooming diode bias
Register output gate bias
Output amplifier source supply
Ground
Symbol
VDD1, VDD2
VST
VDR
VA
VGS
VS
VSS
Min
14.5
2.2
13.5
14.5
2.2
–
–
Typ
15
2.4
14
15
2.4
0
0
Max
15.5
2.6
14.5
15.5
2.6
–
–
Unit
V
V
V
V
V
V
V
Max Current
See
Table 10-
1 on page 7
1 µA
10 µA
10 µA
1 µA
13 mA per
amplifier
–
Table 6-2.
Drive Clock Characteristics
Value
Parameter
Reset gate
High level
Low level
Transfer gate
High level
Low level
Readout register clocks
High level
Readout register frequency
Symbol
ΦR
Min
8.5
-0.1
8.5
-0.1
8.5
–
0
Typ
9
0
9
0
9
10
0
Max
9.5
0.4
9.5
0.4
9.5
25
0
Unit
V
V
V
V
V
MHz
V
Comments
Clock Capacitance ~ 40 pF
ΦP
Clock Capacitance ~ 100 pF
Clock Capacitances
See
Section 7.
ΦL1,2
F
H
If antiblooming operation
inhibited
Exposure time reduction
Pixel saturation adjustment
Antiblooming Gate
ΦA
See
Figure 9-1 on page 7
See
Figure 12-1 on page 9
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TH7818A
7. Clock Capacitances
Figure 7-1.
Clock Capacitances
Φ
L1
Φ
L2
60 pF
170 pF
140 pF
8. Timing Diagrams
The following diagram shows the general clocking scheme.
The line is composed as follows:
Number of prescan pixels
per output
4
Number of useful pixels
per output
512
Total number of pixels
per output
516
Postscan elements may be added in order to either increase the exposure time, or to provide a voltage
reference level.
The following diagram shows the timing for the transfer period.
Figure 8-1.
Line Timing Diagram
Line Period
ΦA
ΦP
ΦL1
ΦL2
ΦR
Transfer Period
ΦR
clock may also be held in high state during line transfer period.
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