NB3N5573
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL Clock
Generator
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Description
The NB3N5573 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 4).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
MARKING
DIAGRAM
16
1
TSSOP−16
DT SUFFIX
CASE 948F
A
L
Y
W
G
1
16
NB3N
5573
ALYWG
G
•
•
•
•
•
•
•
•
•
•
•
Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
External Loop Filter is Not Required
HCSL Differential Output or LVDS with Proper Termination
Four Selectable Multipliers of the Input Frequency
Output Enable with Tri−State Outputs
PCIe Gen1, Gen2, Gen3, Gen4, QPI, UPI Jitter Compliant
Phase Noise: @ 100 MHz
Offset
Noise Power
100 Hz
−109.4 dBc
1 kHz
−127.8 dBc
10 kHz
−136.2 dBc
100 kHz −138.8 dBc
1 MHz
−138.2 dBc
10 MHz −161.4 dBc
20 MHz −163.00 dBc
Typical Period Jitter RMS of 1.5 ps
Operating Range 3.3 V
±10%
Industrial Temperature Range −40°C to +85°C
These are Pb−Free Devices
VDD
X1/CLK
25 MHz Clock or
Crystal
Clock Buffer
Crystal Oscillator
X2
BM
Phase
Detector
Charge
Pump
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
CLK0
VCO
HSCL
Output
HSCL
Output
CLK0
CLK1
CLK1
GND
S0
S1
OE
IREF
Figure 1. NB3N5573 Simplified Logic Diagram
©
Semiconductor Components Industries, LLC, 2017
1
March, 2017 − Rev. 11
Publication Order Number:
NB3N5573/D
NB3N5573
S0
S1
NC
X1/CLK
X2
OE
GND
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
CLK0
CLK0
GND
VDD
CLK1
CLK1
IREF
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
12, 16
4
5
6
7, 13
9
11
10
15
14
3, 8
Symbol
S0
S1
V
DD
X1/CLK
X2
OE
GND
I
REF
CLK1
CLK1
CLK0
CLK0
NC
I/O
Input
Input
Power Supply
Input
Input
Input
Power Supply
Output
HCSL or
LVDS Output
HCSL or
LVDS Output
HCSL or
LVDS Output
HCSL or
LVDS Output
Description
LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to V
DD
. See output select
table 2 for details.
LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to V
DD
. See output select
Table 2 for details.
Positive supply voltage pins are connected to +3.3 V supply voltage.
Crystal or Clock input. Connect to 25 MHz crystal source or single−ended clock.
Crystal input. Connect to a 25 MHz crystal or leave unconnected for clock input.
Output enable tri−states output when connected to GND. Internal pullup resistor to V
DD
.
Ground 0 V. These pins provide GND return path for the devices.
Output current reference pin. Precision resistor (typ. 475
W)
is connected to set the output
current.
Noninverted clock output. (For LVDS levels see Figure 4)
Inverted clock output. (For LVDS levels see Figure 4)
Noninverted clock output. (For LVDS levels see Figure 4)
Inverted clock output. (For LVDS levels see Figure 4)
Do not connect
Table 2. OUTPUT FREQUENCY SELECT TABLE
WITH 25MHz CRYSTAL
S1*
L
L
H
H
S0*
L
H
L
H
CLK Multiplier
1x
4x
5x
8x
f
CLKout
(MHz)
25
100
125
200
Recommended Crystal Parameters
*Pins S1 and S0 default high when left open.
Crystal
Frequency
Load Capacitance
Shunt Capacitance, C0
Equivalent Series Resistance
Initial Accuracy at 25
°C
Temperature Stability
Aging
Drive Level
Fundamental AT−Cut
25 MHz
16−20 pF
7 pF Max
50
W
Max
±20
ppm
±30
ppm
±20
ppm
100
mW
Max
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NB3N5573
Table 3. ATTRIBUTES
Characteristic
ESD Protection
RPU − OE, S0 and S1 Pull−up Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Value
> 2 kV
100 kW
Level 1
UL 94 V−0 @ 0.125 in
7623
Table 4. MAXIMUM RATINGS
(Note 2)
Symbol
V
DD
V
I
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Input Voltage (V
IN
)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
0 lfpm
500 lfpm
(Note 3)
TSSOP–16
TSSOP–16
TSSOP−16
Condition 1
GND = 0 V
GND = 0 V
GND
v
V
I
v
V
DD
Condition 2
Rating
4.6
−0.5 V to V
DD
+0.5 V
−40 to +85
−65 to +150
138
108
33 to 36
265
Unit
V
V
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS
(V
DD
= 3.3 V
±10%,
GND = 0 V, T
A
= −40°C to +85°C, Note 4)
Symbol
VDD
I
DD
I
DDOE
V
IH
V
IL
V
OH
V
OL
V
cross
DV
cross
Power Supply Voltage
Power Supply Current
Power Supply Current when OE is Set Low
Input HIGH Voltage (X/CLK, S0, S1, and OE)
Input LOW Voltage (X/CLK, S0, S1, and OE)
Output HIGH Voltage for HCSL Output (See Figure 5)
Output LOW Voltage for HCSL Output (See Figure 5)
Crossing Voltage Magnitude (Absolute) for HCSL Output
Change in Magnitude of V
cross
for HCSL Output
2000
GND − 300
660
−150
250
700
0
Characteristic
Min
2.97
Typ
3.3
120
Max
3.63
135
65
V
DD
+ 300
800
850
150
550
150
Unit
V
mA
mA
mV
mV
mV
mV
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Measurement taken with outputs terminated with R
S
= 33.2
W,
R
L
= 49.9
W,
with test load capacitance of 2 pF and current biasing resistor
set at 475
W.
See Figure 3.
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NB3N5573
Table 6. AC CHARACTERISTICS
(V
DD
= 3.3 V
±10%,
GND = 0 V, T
A
= −40°C to +85°C; Note 5)
Symbol
f
CLKIN
f
CLKOUT
q
NOISE
Characteristic
Clock/Crystal Input Frequency
Output Clock Frequency
Phase−Noise Performance
f
CLKx
= 200 MHz/100 MHz
@ 100 Hz offset from carrier
@ 1 kHz offset from carrier
@ 10 kHz offset from carrier
@ 100 kHz offset from carrier
@ 1 MHz offset from carrier
@ 10 MHz offset from carrier
t
JITTER
Period Jitter Peak−to−Peak (Note 6)
Period Jitter RMS (Note 6)
Cycle−Cycle RMS Jitter (Note 7)
Cycle−to−Cycle Peak to Peak Jitter (Note 7)
t
JIT(F)
OE
t
DUTY_CYCLE
t
R
t
F
Dt
R
Dt
F
Stabilization
Time
f
CLKx
= 200 MHz
f
CLKx
= 200 MHz
f
CLKx
= 200 MHz
f
CLKx
= 200 MHz
−103/−109
−118/−127.8
−122/−136.2
−130/−138.8
−132/−138.2
−149/−164
10
1.5
2
20
0.4
10
45
175
175
50
340
340
55
700
700
125
125
3.0
20
3
5
35
ps
ps
ms
%
ps
ps
ps
ps
ms
ps
25
Min
Typ
25
200
Max
Unit
MHz
MHz
dBc/Hz
Additive Phase RMS Jitter, Integration Range 12 kHz to 20 MHz
Output Enable/Disable Time
Output Clock Duty Cycle (Measured at cross point)
Output Risetime (Measured from 175 mV to 525 mV, Figure 5)
Output Falltime (Measured from 525 mV to 175 mV, Figure 5)
Output Risetime Variation (Single−Ended)
Output Falltime Variation (Single−Ended)
Stabilization Time From Powerup V
DD
= 3.3 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Measurement taken from differential output on single−ended channel terminated with R
S
= 33.2
W,
R
L
= 49.9
W,
with test load capacitance
of 2 pF and current biasing resistor set at 475
W.
See Figure 3.
6. Sampled with 10000 cycles.
7. Sampled with 1000 cycles.
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NB3N5573
Table 7. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
Symbol
t
jphPCIeG1
Parameter
Conditions
(Notes 8 and 9)
PCIe Gen 1 (Notes 10 and 11)
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 10)
t
jphPCIeG2
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Note 10)
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 10)
RMS Phase Jitter
PCIe Gen 4
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 10)
UPI
(9.6 Gb/s, 10.4 Gb/s or 11.2 Gb/s, 100 MHz, 12 UI)
QPI & SMI
(100.00 MHz or 133.33 MHz,
4.8 Gb/s, 6.4 Gb/s 12UI) (Note 12)
t
jphQPI_SMI
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Note 12)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Note 12)
Min
Typ
10
0.2
Max
16
0.25
Industry
Limit
86
3
Unit
ps (p−p)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
0.9
1.2
3.1
t
jphPCIeG3
0.2
0.3
1
t
jphPCIeG4
0.21
0.3
0.5
t
jphUPI
0.62
0.7
1.0
0.1
0.3
0.5
0.1
0.07
0.15
0.1
0.3
0.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Applies to all outputs.
9. Guaranteed by design and characterization, not tested in production
10. See http://www.pcisig.com for complete specs
11. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
12. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
HCSL INTERFACE
NB3N5573 CLK0
R
L
= 33.2
W
R
L
= 33.2
W
CLK0
Z
o
= 50
W
R
L
= 49.9
W
HCSL
Driver
CLK1
R
L
= 33.2
W
R
L
= 33.2
W
CLK2
IREF
R
REF
= 475
W
Z
o
= 50
W
R
L
= 49.9
W
R
L
= 49.9
W
Z
o
= 50
W
R
L
= 49.9
W
HCSL
Receiver
Z
o
= 50
W
Figure 3. Typical Termination for Output Driver and Device Evaluation
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