19-2093; Rev 1; 2/07
KIT
ATION
EVALU
BLE
AVAILA
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
Features
♦
Single 3V Operation
♦
Excellent Dynamic Performance
59dB SNR at f
IN
= 20MHz
73dB SFDR at f
IN
= 20MHz
♦
Low Power
82mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦
0.02dB Gain and 0.25° Phase Matching (typ)
♦
Wide ±1V
P-P
Differential Analog Input Voltage
Range
♦
400MHz, -3dB Input Bandwidth
♦
On-Chip 2.048V Precision Bandgap Reference
♦
User-Selectable Output Format—Two’s
Complement or Offset Binary
♦
48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
♦
Evaluation Kit Available
MAX1181
The MAX1181 is a 3V, dual 10-bit, analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, nine-
stage ADCs. The MAX1181 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation, and digital communication applica-
tions. The MAX1181 operates from a single 2.7V to 3.6V
supply, consuming only 246mW, while delivering a typi-
cal signal-to-noise ratio (SNR) of 59dB at an input fre-
quency of 20MHz and a sampling rate of 80Msps. The
T/H driven input stages incorporate 400MHz (-3dB)
input amplifiers. The converters may also be operated
with single-ended inputs. In addition to low operating
power, the MAX1181 features a 2.8mA sleep mode, as
well as a 1µA power-down mode to conserve power
during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or external
reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1181 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1181 is available in a 7mm
✕
7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1181 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1182
datasheet for 65Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
Ordering Information
PART
MAX1181ECM
MAX1181ECM+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
48 TQFP-EP*
*EP
= Exposed paddle.
+Denotes
a lead-free package.
Pin Configuration
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
48
47
46
45
44
43
42
41
40
39
38
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Undersampling
Instrumentation
Video Application
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
MAX1181
EP*
26
25
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
V
DD
GND
T/B
SLEEP
PD
OE
D9B
D8B
D7B
GND
V
DD
48 TQFP-EP
Functional Diagram appears at end of data sheet.
NOTE:
THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED
BY A "+" SIGN.
________________________________________________________________
Maxim Integrated Products
D6B
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1181
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, CLK,
COM to GND ...........................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B, D9A–D0A,
D9B–D0B to OGND ..............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ...2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 83.333MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Differential Input Voltage Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
(Note 3)
Signal-to-Noise And Distortion
(Note 3)
Spurious-Free Dynamic
Range (Note 3)
Third-Harmonic Distortion
(Note 3)
SNR
f
INA or B
= 7.47MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz
f
INA or B
= 7.47MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz
f
INA or B
= 7.47MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
fINA or B
= 39.9MHz
f
INA or B
= 7.47MHz
f
INA or B
= 20MHz
f
INA or B
= 39.9MHz
56.5
56
56
55.3
65
64
59.5
59
59
59
58.5
58.5
75
73
71
-76
-76
-75
dB
f
CLK
80
5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±
0.5
25
5
V
V
kΩ
pF
INL
DNL
f
IN
= 7.47MHz
f
IN
= 7.47MHz, no missing codes guaranteed
-2
0
10
±0.6
±0.4
±2.2
±1.0
+2
±2
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINAD
dB
SFDR
dBc
HD3
dBc
2
_______________________________________________________________________________________
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1181
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 83.333MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Total Harmonic Distortion
(First Four Harmonics) (Note 3)
Intermodulation Distortion
(First Five Odd-Order IMDs)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
REFIN Input Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
REFOUT
TC
REF
2.048
±3%
60
1.25
V
REFIN
V
REFP
V
REFN
ΔV
REF
R
REFIN
I
SOURCE
I
SINK
I
SOURCE
I
SINK
ΔV
REF
= V
REFP
- V
REFN
0.95
2.048
2.012
0.988
1.024
> 50
>5
250
250
>5
1.10
V
ppm/°C
mV/mA
V
V
V
V
MΩ
mA
µA
µA
mA
INA+ = INA- = INB+ = INB- = COM
FPBW
t
AD
t
AJ
For 1.5 x full-scale input
SYMBOL
THD
CONDITIONS
f
INA or B
= 7.47MHz, T
A
= +25°C
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz
IMD
f
INA or B
= 38.1546MHz at -6.5dBFS
f
INA or B
= 41.9532MHz at -6.5dBFS
(Note 4)
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
TYP
-73
-70
-70
-73.5
500
400
1
2
2
±1
±0.25
0.2
dBc
MHz
MHz
ns
ps
RMS
ns
%
degrees
LSB
RMS
MAX
-64
-63
dBc
UNITS
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= 2.048V)
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN and COM )
REFP, REFN Input Resistance
R
REFP,
R
REFN
Measured between REFP and COM and
REFN and COM
4
kΩ
_______________________________________________________________________________________
3
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1181
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 83.333MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Differential Reference Input
Voltage
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
SYMBOL
ΔV
REF
V
COM
V
REFP
V
REFN
CONDITIONS
ΔV
REF
= V
REFP
- V
REFN
MIN
TYP
1.024
±
10%
V
DD
/ 2
±
10%
V
COM
+
ΔV
REF
/ 2
V
COM
-
ΔV
REF
/ 2
0.8 x
V
DD
0.8 x
OV
DD
0.2 x
V
DD
0.2 x
OV
DD
0.1
V
IH
= OV
DD
or V
DD
(CLK)
V
IL
= 0
5
I
SINK
= 200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
2.7
1.7
Operating, f
INA or B
= 20MHz at -0.5dBFS
Analog Supply Current
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF , f
INA or B
= 20MHz at
-0.5dBFS
Output Supply Current
I
OVDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 20MHz at -0.5dBFS
Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
5
3.0
2.5
82
2.8
1
13
100
2
246
8.4
3
45
10
291
15
3.6
3.6
97
OV
DD
- 0.2
±10
0.2
±5
±5
MAX
UNITS
V
V
V
V
DIGITAL INPUTS (CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
Input Hysteresis
Input Leakage
Input Capacitance
Output-Voltage Low
Output-Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
DD
OV
DD
V
V
mA
µA
mA
µA
mW
µW
V
HYST
I
IH
I
IL
C
IN
V
OL
V
OH
I
LEAK
C
OUT
V
V
V
µA
pF
V
V
µA
pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
4
_______________________________________________________________________________________
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 1), f
CLK
= 83.333MHz, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Power Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse-Width High
CLK Pulse-Width Low
Wake-Up Time (Note 6)
t
DO
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
Figure 3 (Note 5)
Figure 4
Figure 4
Figure 3 clock period: 12ns
Figure 3 clock period: 12ns
Wakeup from sleep mode
Wakeup from shutdown
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
f
INA or B
= 20MHz at -0.5dBFS
5
10
1.5
6
±1
6
±1
0.28
1.5
-70
0.02
0.25
±0.2
8
ns
ns
ns
ns
ns
µs
SYMBOL
PSRR
Offset
Gain
CONDITIONS
MIN
TYP
±0.2
±0.1
MAX
UNITS
mV/V
%/V
MAX1181
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
dB
dB
degrees
Note 1:
Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
Note 2:
Specifications at
≥
+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a +1.024V full-scale
input voltage range.
Note 4:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5:
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 6:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Typical Operating Characteristics
(V
DD
= 3V, OV
DD
= 2.5V, internal reference, differential input at -0.5dBFS, f
CLK
= 80.0006MHz, C
L
≈
10pF. T
A
= +25°C, unless other-
wise noted.)
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
MAX1181 toc01
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
MAX1181 toc02
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
CHA
f
INA
= 19.9123MHz
f
INB
= 24.9123MHz
f
CLK
= 80.0006MHz
A
INA
= -0.52dBFS
MAX1181 toc03
0
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
0
5
10
15
20
25
30
35
CHA
f
INA
= 6.0449MHz
f
INB
= 7.5099MHz
f
CLK
= 80.0006MHz
A
INA
= -0.46dBFS
0
-10
-20
AMPLITUDE (dB)
-30
-40
-50
-60
-70
-80
-90
-100
CHB
f
INA
= 6.0449MHz
f
INB
= 7.5099MHz
f
CLK
= 80.0006MHz
A
INB
= -0.52dBFS
0
40
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
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