74ALVCH16245
Low−Voltage 16−Bit
Transceiver with Bus Hold
1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16245 is an advanced performance, non−inverting
16−bit transceiver. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16245 is designed with byte control. It can be
operated as two separate octals, or with the controls tied together, as a
16−bit wide function. The Transmit/Receive (T/Rn) inputs determine
the direction of data flow through the bi−directional transceiver.
Transmit (active−HIGH) enables data from A ports to B ports; Receive
(active−LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition. The data inputs include active bushold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
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MARKING DIAGRAM
48
48
1
74ALVCH16245DT
AWLYYWW
TSSOP−48
DT SUFFIX
CASE 1201
A
Location
WL
YY
WW
1
= Assembly
= Wafer Lot
= Year
= Work Week
•
Designed for Low Voltage Operation: V
CC
= 1.65
−
3.6 V
•
3.6 V Tolerant Inputs and Outputs
•
High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
•
•
•
•
•
•
•
•
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive:
±24
mA Drive at 3.0 V
±12
mA Drive at 2.3 V
±4
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
†
Near Zero Static Supply Current in All Three Logic States (40
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
±250
mA @ 125°C
ESD Performance: Human Body Model >2000V; Machine Model >200V
Second Source to Industry Standard 74ALVCH16245
ORDERING INFORMATION
Device
74ALVCH16245DTR
Package
TSSOP
Shipping
2500/Tape & Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to V
CC
through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 2
1
Publication Order Number:
74ALVCH16245/D
74ALVCH16245
1
T/R1 1
B0 2
B1 3
GND 4
B2 5
B3 6
V
CC
7
B4 8
B5 9
GND 10
B6 11
B7 12
B8 13
B9 14
GND 15
B10 16
B11 17
V
CC
18
B12 19
B13 20
GND 21
B14 22
B15 23
T/R2 24
48 OE1
47 A0
46 A1
45 GND
44 A2
43 A3
42 V
CC
41 A4
40 A5
39 GND
38 A6
37 A7
36 A8
35 A9
34 GND
33 A10
32 A11
31 V
CC
30 A12
29 A13
28 GND
27 A14
26 A15
25 OE2
T/R1
48
OE1
25
OE2
24
T/R2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
1
24
T/R2
48
25
T/R1
OE1
OE2
A0:7
B0:7
A8:15
B8:15
One of Eight
Figure 2. Logic Diagram
EN1
EN2
EN3
EN4
1
1
∇
2
3
5
6
8
9
11
2
∇
3
∇
12
13
14
16
Figure 1. 48−Lead Pinout
(Top View)
PIN NAMES
Pins
OEn
T/Rn
A0−A15
B0−B15
Function
Output Enable Inputs
Transmit/Receive Inputs
Side A Inputs or 3−State Outputs
Side B Inputs or 3−State Outputs
4
∇
17
19
20
22
23
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Figure 3. IEC Logic Diagram
Inputs
OE1
L
L
H
T/R1
L
H
X
Outputs
Bus B0:7 Data to Bus A0:7
Bus A0:7 Data to Bus B0:7
High Z State on A0:7, B0:7
Inputs
OE2
L
L
H
T/R2
L
H
X
Outputs
Bus B8:15 Data to Bus A8:15
Bus A8:15 Data to Bus B8:15
High Z State on A8:15, B8:15
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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2
74ALVCH16245
MAXIMUM RATINGS
(Note 1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30 to 35
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Above V
CC
and Below GND at 125°C (Note 6)
V
I
< GND
V
O
< GND
Parameter
Value
*0.5
to
)4.6
*0.5
to
)4.6
*0.5
to
)4.6
*50
*50
$50
$100
$100
*65
to
)150
260
)150
90
Level 1
UL 94 V−O @ 0.125 in
u2000
u200
N/A
$250
V
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
I
LATCH−UP
Latch−Up Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 2.5 V
$
V
CC
= 3.0 V
$
0.2 V
0.3 V
Parameter
Operating
Data Retention Only
(Note 7)
(Active State)
(3−State)
Min
2.3
1.5
−0.5
0
0
*40
0
0
Max
3.6
3.6
3.6
V
CC
3.6
)85
20
10
Unit
V
V
V
°C
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
74ALVCH16245
DC ELECTRICAL CHARACTERISTICS
T
A
=
*405C
to
)855C
Symbol
V
IH
Parameter
HIGH Level Input Voltage
(Note 8)
1.65 V
v
V
CC
t
2.3 V
2.3 V
v
V
CC
v
2.7 V
2.7 V
t
V
CC
v
3.6 V
V
IL
LOW Level Input Voltage
(Note 8)
1.65 V
v
V
CC
t
2.3 V
2.3 V
v
V
CC
v
2.7 V
2.7 V
t
V
CC
v
3.6 V
V
OH
HIGH Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OH
=
*100
mA
V
CC
= 1.65 V; I
OH
=
*4
mA
V
CC
= 2.3 V; I
OH
=
*6
mA
V
CC
= 2.3 V; I
OH
=
*12
mA
V
CC
= 2.7 V; I
OH
=
*12
mA
V
CC
= 3.0 V; I
OH
=
*12
mA
V
CC
= 3.0 V; I
OH
=
*24
mA
V
OL
LOW Level Output Voltage
1.65 V
v
V
CC
v
3.6 V; I
OL
= 100
mA
V
CC
= 1.65 V; I
OL
= 4 mA
V
CC
= 2.3 V; I
OL
= 6 mA
V
CC
= 2.3 V; I
OL
= 12 mA
V
CC
= 2.7 V; I
OL
= 12 mA
V
CC
= 3.0 V; I
OL
= 24 mA
I
I
I
I(HOLD)
Input Leakage Current
Minimum Bus−hold Input
Current
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
I
v
3.6 V
V
CC
= 3.6 V; V
IN
= 0 to 3.6 V
V
CC
= 3.0 V, V
IN
= 0.8 V
V
CC
= 3.0 V, V
IN
= 2.0 V
V
CC
= 2.3 V, V
IN
= 0.7 V
V
CC
= 2.3 V, V
IN
= 1.7 V
V
CC
= 1.65 V, V
IN
= 0.58 V
V
CC
= 1.65 V, V
IN
= 1.07 V
I
OZ
I
OFF
I
CC
3−State Output Current
Power−Off Leakage Current
Quiescent Supply Current
(Note 9)
Increase in I
CC
per Input
1.65 V
v
V
CC
v
3.6 V; 0 V
v
V
O
v
3.6 V; V
I
= V
IH
or V
IL
V
CC
= 0 V; V
I
or V
O
= 3.6 V
1.65 V
v
V
CC
v
3.6 V; V
I
= GND or V
CC
1.65 V
v
V
CC
v
3.6 V; 3.6 V
v
V
I
, V
O
v
3.6 V
2.7 V
t
V
CC
≤
3.6 V; V
IH
= V
CC
*
0.6 V
75
*75
45
*45
25
*25
$10
10
40
$40
750
mA
mA
mA
mA
V
CC
*
0.2
1.2
2.0
1.7
2.2
2.4
2.0
0.2
0.45
0.4
0.7
0.4
0.55
$5.0
$500
mA
mA
V
Condition
0.65
1.7
2.0
0.35
0.7
0.8
V
V
CC
V
Min
V
CC
Max
Unit
V
DI
CC
8. These values of V
I
are used to test DC electrical characteristics only.
9. Outputs disabled or 3−state only.
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74ALVCH16245
AC CHARACTERISTICS
(Note 10; t
R
= t
F
= 2.0 ns; C
L
= 30 pF; R
L
= 500
W)
Limits
T
A
=
−40°C
to +85°C
V
CC
= 3.0 V to 3.6 V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Parameter
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 11)
Waveform
1
2
2
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.0
3.0
4.4
4.4
4.1
4.1
0.5
0.5
V
CC
= 2.3 V to 2.7 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.7
3.7
5.7
5.7
5.2
5.2
0.5
0.5
V
CC
= 1.65 V to1.95 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
6.0
6.0
9.3
9.3
7.6
7.6
0.75
0.75
Unit
ns
ns
ns
ns
10. For C
L
= 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Condition
Note 12
Note 12
Note 12, 10MHz
Typical
6
7
20
Unit
pF
pF
pF
12. V
CC
= 1.8, 2.5 or 3.3 V; V
I
= 0 V or V
CC
.
V
IH
An, Bn
Vm
t
PLH
Bn, An
Vm
WAVEFORM 1 − PROPAGATION DELAYS
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
V
IH
OEn, T/Rn
t
PZH
An, Bn
Vm
≈
0V
t
PZL
An, Bn
Vm
Vx
V
OL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
t
R
= t
F
= 2.0 ns, 10% to 90%; f = 1 MHz; t
W
= 500 ns
t
PLZ
≈
V
CC
Vm
t
PHZ
Vm
0V
V
OH
Vy
Vm
0V
t
PHL
Vm
V
OL
V
OH
Figure 4. AC Waveforms
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