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74LVX32M

产品描述LV/LV-A/LVX/H SERIES, QUAD 2-INPUT OR GATE, PDSO14
产品类别逻辑    逻辑   
文件大小107KB,共8页
制造商ST(意法半导体)
官网地址http://www.st.com/
标准
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74LVX32M概述

LV/LV-A/LVX/H SERIES, QUAD 2-INPUT OR GATE, PDSO14

LV/LV-A/LVX/H系列, 四 2输入 或门, PDSO14

74LVX32M规格参数

参数名称属性值
是否Rohs认证符合
厂商名称ST(意法半导体)
零件包装代码SOIC
包装说明SOP, SOP14,.25
针数14
Reach Compliance Codecompliant
系列LV/LV-A/LVX/H
JESD-30 代码R-PDSO-G14
JESD-609代码e4
长度8.65 mm
负载电容(CL)50 pF
逻辑集成电路类型OR GATE
最大I(ol)0.004 A
湿度敏感等级1
功能数量4
输入次数2
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP14,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE
电源3.3 V
Prop。Delay @ Nom-Sup12.5 ns
传播延迟(tpd)18 ns
认证状态Not Qualified
施密特触发器NO
座面最大高度1.75 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
宽度3.9 mm
Base Number Matches1

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74LVX32
LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED :
t
PD
= 4.4ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL :
V
IL
=0.8V, V
IH
=2V AT V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX32M
T&R
74LVX32MTR
74LVX32TTR
DESCRIPTION
The 74LVX32 is a low voltage CMOS QUAD
2-INPUT OR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
The internal circuit is composed of 2 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/8

 
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