S i531 7
P
I N
-C
O N T R O L L E D
1–711 MH
Z
J
I T T E R
C
L E A N I N G
C
L O C K
Features
Provides jitter attenuation for any clock
frequency
One clock input / two clock outputs
Input/output frequency range:
1–711 MHz
Ultra low jitter: 300 fs
(12 kHz–20 MHz) typical
Simple pin control interface
Selectable loop bandwidth for jitter
attenuation: 60 Hz–8.4 kHz
Meets OC-192 GR-253-CORE jitter
specifications
Selectable output clock signal
format: LVPECL, LVDS, CML or
CMOS
Single supply: 1.8, 2.5, or 3.3 V
Loss of lock and loss of signal
alarms
VCO freeze during LOS/LOL
On-chip voltage regulator with high
PSRR
Small size: 6 x 6 mm, 36-QFN
Wide temperature range: –40 to
+85 ºC
Ordering Information:
See page 40.
Applications
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH
Switches and routers
Medical instrumentation
Test and measurement
Pin Assignments
Description
The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications
that require jitter attenuation without clock multiplication. The Si5317 accepts a
single clock input ranging from 1 to 711 MHz and generates two low jitter clock
outputs at the same frequency. The clock frequency range and loop bandwidth are
selectable from a simple look-up table. The Si5317 is based on Silicon
Laboratories' 3rd-generation DSPLL
®
technology, which provides jitter attenuation
on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is user
selectable, providing jitter performance optimization at the application level.
Functional Block Diagram
Rev. 1.1 4/11
Copyright © 2011 by Silicon Laboratories
Si5317
Si5317
T
A B L E O F
C
O N T E N T S
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Frequency Range Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Output Skew Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5. VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. Input Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2. Output Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
7. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9. Pin Descriptions: Si5317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
12. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13. Si5317 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.1
3
Si5317
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T
A
V
DD
Test Condition
3.3 V nominal
2.5 V nominal
1.8 V nominal
Min
–40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
ºC
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Supply Current (Supply
current is independent of
V
DD
)
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
1
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled
1
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
2
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled
2
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Min
—
Typ
251
Max
279
Units
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
CKIN Input Pin
Input Common Mode
Voltage
(Input Threshold Voltage)
Input Resistance
Input Voltage Level Limits
Single-ended Input Voltage
Swing
V
ICM
0.9
1.0
1.1
20
0
0.2
0.25
—
—
—
40
—
—
—
1.4
1.7
1.95
60
V
DD
—
—
V
V
V
k
V
V
PP
V
PP
CKN
RIN
CKN
VIN
V
ISE
Single-ended
See note
3
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
Notes:
1.
LVPECL outputs require VDD > 2.25 V.
2.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3.
No overshoot or undershoot.
4
Rev. 1.1
Si5317
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Differential Input
Voltage Swing
Symbol
V
ID
Test Condition
f
CKIN
< 212.5 MHz
See Figure 2.
f
CKIN
> 212.5 MHz
See Figure 2.
Min
0.2
0.25
Typ
—
—
Max
—
—
Units
V
PP
V
PP
CKOUT Output Clock
1
Common Mode
Differential Output Swing
Single-ended Output Swing
Differential Output Voltage
Common Mode
Output Voltage
Differential
Output Voltage
V
OCM
V
OD
V
SE
CKO
VD
CKO
VCM
CKO
VD
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load
line-to-line
CML 100
load
line-to-line
LVDS 100
load
line-to-line
Low swing LVDS 100
load
line-to-line
Common Mode
Output Voltage
Output Voltage Low
Output Voltage High
Output Drive Current
CKO
VCM
CKO
VOLLH
CKO
VOHLH
CKO
IO
LVDS 100
load
line-to-line
CMOS
V
DD
= 1.71 V
CMOS
CMOS
Driving into CKO
VOL
for out-
put low or CKO
VOH
for output
high. CKOUT+ and CKOUT–
shorted externally.
V
DD
= 1.8 V
V
DD
= 3.3 V
2-Level LVCMOS Input Pins
Input Voltage Low
V
IL
V
DD
= 1.71 V
V
DD
= 2.25 V
V
DD
= 2.97 V
—
—
—
—
—
—
0.5
0.7
0.8
V
V
V
—
—
7.5
32
—
—
mA
mA
V
DD
–
1.42
1.1
0.5
350
—
500
350
1.125
—
0.8 x V
DD
—
—
—
425
V
DD
–
0.36
700
425
1.2
—
—
V
DD
–
1.25
1.9
0.93
500
—
900
500
1.275
0.4
—
V
V
PP
V
PP
mV
PP
V
mV
PP
mV
PP
V
V
V
Notes:
1.
LVPECL outputs require VDD > 2.25 V.
2.
This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3.
No overshoot or undershoot.
Rev. 1.1
5
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