HY62UF8400A/ HY62QF8400A/ HY62EF8400A/
HY62SF8400A Series
512Kx8bit full CMOS SRAM
PRELIMINARY
DESCRIPTION
The
HY62UF8400A
/
HY62QF8400A
/
HY62EF8400A / HY62SF8400A is a high speed
and super low power 4Mbit full CMOS SRAM
organized as 524,288 words by 8 bits. The
HY62UF8400A / HY62QF8400A / HY62EF8400A
/ HY62SF8400A uses high performance full
CMOS process technology and is designed for
high speed and low power circuit technology. It is
particularly well-suited for the high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 1.5V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
- 1.5V(min) data retention
•
Standard pin configuration
- 48ball uBGA
Product
Voltage
Speed
Operation
Standby Current(uA)
No.
(V)
(ns)
Current(mA)
LL
SL
HY62UF8400A
3.0
55/70/85
10
20
4
HY62UF8400A-I
3.0
55/70/85
10
20
4
HY62QF8400A
2.5
70/85/100
5
20
4
HY62QF8400A-I
2.5
70/85/100
5
20
4
HY62EF8400A
2.0
85/100/120
5
20
4
HY62EF8400A-I
2.0
85/100/120
5
20
4
HY62SF8400A
1.8
100/120/150
5
20
4
HY62SF8400A-I
1.8
100/120/150
5
20
4
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
Temperature
(°C)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
0~70(Normal)
-40~85(E.T.)
PIN CONNECTION
( Top View )
A0
A1
CS2 A3
/WE A4
NC
A5
A6
A7
A8
IO1
IO2
Vcc
Vss
A18 A17
IO3
A18
CONTROL
LOGIC
/CS1
CS2
/WE
/OE
A0
ADD INPUT BUFFER
COLUMN DECODER
BLOCK DIAGRAM
SENSE AMP
ROW DECODER
I/O1
DATA I/O BUFFER
I/O8
IO5 A2
IO6
Vss
Vcc
IO7
IO8 /OE /CS1 A16 A15 IO4
A9
A10 A11 A12 A13 A14
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Pin Name
A0 ~ A18
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Address Input
Data Input/Output
Power(3.0V, 2.5V, 2.0V or 1.8V)
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Feb. 99
Hyundai Semiconductor
WRITE DRIVER
MEMORY ARRAY
2048x2048
HY62UF8400A/HY62QF8400A/HY62EF8400A/HY62SF8400A Series
ORDERING INFORMATION
Part No.
HY62UF8400ALLM
HY62UF8400ASLM
HY62UF8400ALLM-I
HY62UF8400ASLM-I
HY62QF8400ALLM
HY62QF8400ASLM
HY62QF8400ALLM-I
HY62QF8400ASLM-I
HY62EF8400ALLM
HY62EF8400ASLM
HY62EF8400ALLM-I
HY62EF8400ASLM-I
HY62SF8400ALLM
HY62SF8400ASLM
HY62SF8400ALLM-I
HY62SF8400ASLM-I
Speed
55/70/85
55/70/85
55/70/85
55/70/85
70/85/100
70/85/100
70/85/100
70/85/100
85/100/120
85/100/120
85/100/120
85/100/120
100/120/150
100/120/150
100/120/150
100/120/150
Power
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
Temp.
Package
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
uBGA
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
E.T.
Note 1. E.T. : Extended Temperature, Blank : Normal Temperature
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Rating
-0.2 to 3.6
-0.2 to 4.0
0 to 70
Unit
V
V
°C
Remark
-40 to 85
°C
HY62UF8400A
HY62QF8400A
HY62EF8400A
HY62SF8400A
HY62UF8400A-I
HY62QF8400A-I
HY62EF8400A-I
HY62SF8400A-I
T
STG
P
D
T
SOLDER
Storage Temperature
Power Dissipation
Lead Soldering Temperature & Time
-55 to 150
1.0
260
•
5
°C
W
°C•sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
Rev.02 / Feb. 99
2
HY62UF8400A/HY62QF8400A/HY62EF8400A/HY62SF8400A Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Parameter
Supply Voltage
Product
HY62UF8400A-(I)
HY62QF8400A-(I)
HY62EF8400A-(I)
HY62SF8400A-(I)
HY62UF8400A-(I)
HY62QF8400A-(I)
HY62EF8400A-(I)
HY62SF8400A-(I)
HY62UF8400A-(I)
HY62QF8400A-(I)
HY62EF8400A-(I)
HY62SF8400A-(I)
HY62UF8400A-(I)
HY62QF8400A-(I)
HY62EF8400A-(I)
HY62SF8400A-(I)
Min.
2.7
2.2
1.8
1.6
0
Typ.
3.0
2.5
2.0
1.8
0
Max.
3.3
2.8
2.2
2.0
0
Unit
V
V
V
V
Vss
Ground
V
IH
Input High Voltage
V
IL
Input Low Voltage
2.2
2.0
1.6
1.4
-0.2
(1)
-
-
-
-
Vcc+0.2
Vcc+0.2
Vcc+0.2
Vcc+0.2
0.4
V
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
MODE
Standby
Output Disabled
Read
Write
I/O OPERATION
High-Z
High-Z
Data Out
Data In
Supply Current
Isb, Isb1
Icc
Icc
Icc
Note :
1. H=V
IH
, L=V
IL
, X=don't care
Rev.02 / Feb. 99
3
HY62UF8400A/HY62QF8400A/HY62EF8400A/HY62SF8400A Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 3.0V±10%/2.5V±10%/2.0V±10%/1.8V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.)
Sym
Parameter
Test Condition
Min.
Typ.
Max.
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS1 = V
IH
or
-1
-
1
CS2 = V
IL
or
/
OE
=
V
IH
or /WE = V
IL
Icc
Operating HY62UF8400A-(I) /CS1 = V
IL
,
Vcc = 3.0V
-
5
10
Power
HY62QF8400A-(I) CS2 = V
IH,
Vcc = 2.5V/2V/
-
3
5
Supply
HY62EF8400A-(I) V
IN
= V
IH
or V
IL,
1.8V
Current
HY62SF8400A-(I) I
I/O =
0mA
I
CC1
Average
HY62UF8400A-(I) /CS1 = V
IL
CS2 = V
IH,
-
-
45
Operating HY62QF8400A-(I) Min Duty Cycle = 100%, I
I/O =
0mA
-
-
35
Current
HY62EF8400A-(I)
-
-
25
HY62SF8400A-(I)
-
-
20
I
SB
TTL
HY62UF8400A-(I) /CS1 = V
IH
or CS2 = V
IL
-
-
0.5
Standby
HY62QF8400A-(I)
-
-
0.3
Current
HY62EF8400A-(I)
-
-
0.3
(TTL Input)
HY62SF8400A-(I)
-
-
0.3
I
SB1
Standby Current
/CS1 > Vcc - 0.2V,
SL
-
0.2
4
(CMOS Input)
CS2 > Vcc - 0.2V or
LL
-
-
20
CS2 < 0.2V
V
OL
Output
HY62UF8400A-(I) Vcc = 3.0V
I
OL
= 2.1mA
-
-
0.4
Low
HY62QF8400A-(I) Vcc = 2.5V
I
OL
= 0.5mA
Voltage
HY62EF8400A-(I) Vcc = 2.0V
I
OL
= 0.33mA
HY62SF8400A-(I) Vcc = 1.8V
I
OL
= 0.26mA
V
OH
Output
HY62UF8400A-(I) Vcc = 3.0V
I
OH =
-1.0mA
2.2
-
-
High
HY62QF8400A-(I) Vcc = 2.5V
I
OH =
-0.5mA
2.0
-
-
Voltage
HY62EF8400A-(I) Vcc = 2.0V
I
OH =
-0.44mA
1.6
-
-
HY62SF8400A-(I) Vcc = 1.8V
I
OH =
-0.44mA
1.4
-
-
Note : Typical values are at Vcc = 3.0V/2.5V/2.0V/1.8V, T
A
= 25°C
Unit
uA
uA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
V
V
V
Rev.02 / Feb. 99
4
HY62UF8400A/HY62QF8400A/HY62EF8400A/HY62SF8400A Series
AC CHARACTERISTICS
Vcc = 3.0V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-55
-70
-85
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
55
-
70
-
85
-
2
tAA
Address Access Time
-
55
-
70
-
85
3
tACS
Chip Select Access Time
-
55
-
70
-
85
4
tOE
Output Enable to Output Valid
-
35
-
40
-
45
5
tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
30
8
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
30
9
tOH
Output Hold from Address Change
10
-
10
-
10
-
WRITE CYCLE
10 tWC
Write Cycle Time
55
-
70
-
85
-
11 tCW
Chip Selection to End of Write
50
-
60
-
70
-
12 tAW
Address Valid to End of Write
50
-
60
-
70
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
45
-
50
-
55
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
20
0
25
0
30
17 tDW
Data to Write Time Overlap
25
-
30
-
35
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
5
-
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Vcc = 2.5V±10%, T
A
= 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.), unless otherwise specified
-70
-85
-10
# Symbol
Parameter
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
tRC
Read Cycle Time
70
-
85
-
100
-
2
tAA
Address Access Time
-
70
-
85
-
100
3
tACS
Chip Select Access Time
-
70
-
85
-
100
4
tOE
Output Enable to Output Valid
-
40
-
45
-
50
5
tCLZ
Chip Select to Output in Low Z
10
-
10
-
20
-
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
0
30
8
tOHZ
Out Disable to Output in High Z
0
30
0
30
0
30
9
tOH
Output Hold from Address Change
10
-
10
-
15
-
WRITE CYCLE
10 tWC
Write Cycle Time
70
-
85
-
100
-
11 tCW
Chip Selection to End of Write
60
-
70
-
80
-
12 tAW
Address Valid to End of Write
60
-
70
-
80
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
50
-
55
-
75
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
25
0
30
0
35
17 tDW
Data to Write Time Overlap
30
-
35
-
45
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
5
-
10
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.02 / Feb. 99
5
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