Datasheet> 器件分类 > 存储> 存储> HY27UG084G2M-UCB

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HY27UG084G2M-UCB: 产品描述Flash, 512MX8, 30ns, PBGA52, 12 X 17 MM, 0.65 MM HEIGHT, ULGA-52; 产品类别存储存储; 文件大小438KB，共53页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY27UG084G2M-UCB概述

Flash, 512MX8, 30ns, PBGA52, 12 X 17 MM, 0.65 MM HEIGHT, ULGA-52

HY27UG084G2M-UCB规格参数

参数名称	属性值
是否Rohs认证	不符合
零件包装代码	LGA
包装说明	12 X 17 MM, 0.65 MM HEIGHT, ULGA-52
针数	52
Reach Compliance Code	unknown
ECCN代码	3A991.B.1.A
最长访问时间	30 ns
JESD-30 代码	R-PBGA-B52
长度	17 mm
内存密度	4294967296 bit
内存集成电路类型	FLASH
内存宽度	8
功能数量	1
端子数量	52
字数	536870912 words
字数代码	512000000
工作模式	ASYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	512MX8
封装主体材料	PLASTIC/EPOXY
封装代码	VFLGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
编程电压	3.3 V
认证状态	Not Qualified
座面最大高度	0.65 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	2.7 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BUTT
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
类型	NAND TYPE
宽度	12 mm
Base Number Matches	1

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Preliminary

HY27UG(08/16)4G(2/D)M Series

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash

Document Title

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

Initial Draft.

1) Add Errata

tWH

tWP

tWC

History

Draft Date

May. 13. 2005

Remark

Preliminary

0.1

Specification

Relaxed value

May. 23. 2005

Preliminary

1) Correct the Valid Blocks Number.

0.2

Valid Blocks (max)

Before

After

4,098

4,096

Jun. 13. 2005

Preliminary

1) Add tRSBY (Table 11)

- tRSBY (Dummy Busy Time for Cache Read)

0.3

- tRSBY is 5us (typ.)

2) Edit Figure 18, 19

3) Correct Extended Read Status Register Commands (Table. 19)

1) Add ULGA Package.

- Figures & texts are added.

2) Correct the test Conditions (DC Characteristics table)

Test Conditions (

LI,

)

Before

VIN=VOUT=0 to 3.6V

VIN=VOUT=0 to Vcc (max)

JUn. 14. 2005

Preliminary

0.4

After

Sep. 02. 2005

Preliminary

3) Change AC Conditions table

4) Add tWW parameter ( tWW = 100ns, min)

- Texts & Figures are added.

- tWW is added in AC timing characteristics table.

5) Edit System Interface Using CE don’t care Figures.

6) Correct Address Cycle Map.

Rev 0.5 / Oct. 2005

Preliminary

HY27UG(08/16)4G(2/D)M Series

4Gbit (512Mx8bit / 256Mx16bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27UG(08/16)4G(2/D)M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in

3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP# input pin.

The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-

tiple memories the RB# pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27UG(08/16)4G(2/D)M extended reliability of 100K pro-

gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the

code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-

tion.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,

Read ID2 extension.

The HYNIX HY27UG(08/16)4G(2/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.

1.1 Product List

PART NUMBER

HY27UG084G(2/D)M

HY27UG164G2M

ORIZATION

x16

VCC RANGE

2.7 - 3.6 Volt

PACKAGE

48TSOP1/52-ULGA

48TSOP1

Rev 0.5 / Oct. 2005

HY27UG084G2M-UCB

HY27UG084G2M-UCB概述

HY27UG084G2M-UCB规格参数

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