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74LVC374ABQ,115

产品描述74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state QFN 20-Pin
产品类别逻辑    逻辑   
文件大小278KB,共16页
制造商Nexperia
官网地址https://www.nexperia.com
标准
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74LVC374ABQ,115概述

74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state QFN 20-Pin

74LVC374ABQ,115规格参数

参数名称属性值
Brand NameNexperia
是否Rohs认证符合
零件包装代码QFN
包装说明HVQCCN,
针数20
制造商包装代码SOT764-1
Reach Compliance Codecompliant
系列LVC/LCX/Z
JESD-30 代码R-PQCC-N20
JESD-609代码e4
长度4.5 mm
逻辑集成电路类型BUS DRIVER
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量20
最高工作温度125 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码HVQCCN
封装形状RECTANGULAR
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)260
传播延迟(tpd)10 ns
认证状态Not Qualified
座面最大高度1 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)1.2 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度2.5 mm
Base Number Matches1

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74LVC374A
Rev. 4 — 24 August 2020
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Product data sheet
1. General description
The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The
device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of
their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either
3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and
5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels
I
OFF
circuitry provides partial Power-down mode operation
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC374ABQ,115相似产品对比

74LVC374ABQ,115 74LVC374AD,112 74LVC374AD,118 74LVC374ADB,112 74LVC374ADB,118 74LVC374APW,112 74LVC374APW,118
描述 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state QFN 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SOP 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SOP 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SSOP2 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state SSOP2 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state TSSOP2 20-Pin 74LVC374A - Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state TSSOP2 20-Pin
Brand Name Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
零件包装代码 QFN SOP SOP SSOP2 SSOP2 TSSOP2 TSSOP2
包装说明 HVQCCN, SOP, SOP, SSOP, SSOP, TSSOP, TSSOP,
针数 20 20 20 20 20 20 20
制造商包装代码 SOT764-1 SOT163-1 SOT163-1 SOT339-1 SOT339-1 SOT360-1 SOT360-1
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
系列 LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 代码 R-PQCC-N20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609代码 e4 e4 e4 e4 e4 e4 e4
长度 4.5 mm 12.8 mm 12.8 mm 7.2 mm 7.2 mm 6.5 mm 6.5 mm
逻辑集成电路类型 BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
湿度敏感等级 1 1 1 1 1 1 1
位数 8 8 8 8 8 8 8
功能数量 1 1 1 1 1 1 1
端口数量 2 2 2 2 2 2 2
端子数量 20 20 20 20 20 20 20
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 HVQCCN SOP SOP SSOP SSOP TSSOP TSSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度) 260 260 260 260 260 260 260
传播延迟(tpd) 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns
座面最大高度 1 mm 2.65 mm 2.65 mm 2 mm 2 mm 1.1 mm 1.1 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
标称供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
表面贴装 YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式 NO LEAD GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.5 mm 1.27 mm 1.27 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
端子位置 QUAD DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30 30 30 30 30
宽度 2.5 mm 7.5 mm 7.5 mm 5.3 mm 5.3 mm 4.4 mm 4.4 mm
Base Number Matches 1 1 1 1 1 1 1
是否Rohs认证 符合 符合 符合 符合 符合 - -
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