FM1608S FRAM
®
Memory
65,536-Bit Nonvolatile Ferroelectric RAM
Product Specification
Features
65,536 Bit Bytewide Nonvolatile Ferroelectric RAM
Organized as 8,192 x 8
s
CMOS Technology with Integrated Ferroelectric Storage Cells
s
Fully Synchronous Operation
- 180ns Read Access
- 320ns Read/Write Cycle Time
s
Ultra-High Endurance
- 10 Billion (10
10
) Read/Write Cycle Endurance
s
On Chip Data Protection Circuit
s
10 Year Data Retention without Power
Single 5 Volt ±10% Supply
Low Power Consumption
- Active Current: 25mA
- Standby Current: 50µA
s
CMOS/TTL Compatible I/O Pins
s
28 Pin DIP and SOP Packages
s
-40° to +85°C Ambient Operating Temperature Range
s
s
s
Description
The FM1608S is a bytewide ferroelectric RAM, or FRAM
®
product, organized as 8k x 8. FRAM memory products from Ramtron
combine the read/write characteristics of semiconductor RAM with
nonvolatile data retention.
This product is manufactured in a 0.8-micron Si gate CMOS
technology with the addition of integrated thin film ferroelectric
storage cells developed and patented by Ramtron.
The ferroelectric cells are polarized on each read or write cycle,
therefore no special store or recall sequence is required. The
memory is always static and nonvolatile.
Ramtron's FRAM products operate from a single +5 volt power
supply and are TTL/CMOS compatible on all inputs and outputs. The
FM1608S utilizes the JEDEC standard bytewide SRAM pinout, but
differs slightly in operation due to the integrated address latch.
Functional Diagram
CE
Pin Configuration
Address Latch
Row Decoder
A
3-9,11,12
256 x 256
FRAM
Memory
Array
Column Decoder
A
0-2,10
I/O
0-7
WE
OE
I/O Latch & Buffer
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Ramtron reserves the right to change or discontinue this product without notice.
Address Latch
Control Logic
©
1995 Ramtron International Corporation,
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-FRAM, (719) 481-7000;
Fax
(719) 488-9095
R8 September 1995
Device Operation
Read Operation
When CE is low and WE is high, a read operation is performed
by the FRAM memory. On the falling edge of CE, all address bits (A
0
-
A
12
) are latched into the part and the cycle is started. Data will
appear on the output pins a maximum access time (t
CA
) after the
beginning of the cycle.
The designer should ensure that there are no address transitions
from t
AS
(setup time) before the falling edge of CE to t
AH
(hold time)
after it. After t
AH
, the address pins are ignored for the remainder of
the cycle. It is equally important that CE be generated such that
unwanted glitches or pulses, of any duration, be prevented.
After the read has completed, CE should be brought high for the
precharge interval (t
PC
). During this period data is restored in the
internal memory cells and the chip is prepared for the next read or
write. FRAM memories require CE.
The OE pin may be used to avoid bus conflicts on the system bus.
Only when both CE and OE are low will the FRAM memory drive its
outputs. Under all other circumstances, the output drivers are held in
a high impedance (High-Z) condition. Note that the internal read
operation is performed regardless of the state of the OE pin.
Low Voltage Protection
When V
CC
is below 3.5V (typical), all read and write operations
to the part will be ignored. For systems in which unwanted signal
transitions would otherwise occur on the CE pin at or above this
voltage, CE should be held high with a power supply monitor circuit.
Whenever V
CC
rises above 3.5V, either after power up or a
brownout, no read or write operation will take place until CE has
been high (above V
IH
) for at least a precharge interval (t
PC
). When it
is brought low, an access will start.
Theory of Operation
The FM1608S FRAM memory uses a patented ferroelectric
technology to achieve nonvolatility. Ferroelectric material may be
polarized in one direction or another with the application of an
electric field, and will remain polarized when the field is removed.
They are insensitive to magnetic fields.
The FM1608S is designed with a differential cell architecture, as
shown in the figure below. During a read operation, the word line
and plate enable lines are brought high, transferring charge from the
ferroelectric storage elements to the bit lines. Nonvolatile elements
polarized in the opposite direction to the field will source more
charge than those polarized in the direction of the field. Sense
Write Operation
amplifiers built into the chip compare the two charge magnitudes,
When CE falls while WE is low, or WE falls while CE is low, a
producing a binary value. After the read operation, the data is then
write operation will be performed by the FRAM memory. On the
automatically re-written back into the nonvolatile elements.
falling edge of CE, as in the read cycle, the address will be latched
During the write operation, the sense amplifiers drive the bit
into the part with the same setup and hold requirements. As in the
lines to the state of the data input pins. The word line is enabled and
read cycle, CE must be held high for a precharge interval (t
PC
)
the place enable line is pulsed, polarizing each of the complementary
between each access.
nonvolatile storage elements in the appropriate direction.
Data is latched into the part on the rising edge of WE or CE,
The part may be read or written a total of 10 billion (10
10
)
whichever occurs first. Write operations take place regardless of the
cycles without degrading the data retention of the device. Operation
state of OE, however, it may need to be driven high by the system at
of the part beyond this limit will eventually result in nonvolatile data
the beginning of the cycle in order to avoid bus conflicts.
There is no long internal write delay after a write operation. Data retention failure.
is immediately nonvolatile and power may be removed from the part
upon completion of the precharge interval following the write.
FRAM Memory Cell
Bit Line True
Bit Line Complement
Word Line
Plate
Enable
Ferroelectric Capacitors
2
Absolute Maximum Ratings
(1)
(Beyond Which Permanent Damage Could Result)
Description
Ambient Storage or Operating Temperature to
Guarantee Nonvolatility of Stored Data
Voltage on Any Pin with Respect to Ground
Lead Temperature (Soldering, 10 Seconds)
Ratings
-40 to +85°C
-1.0 to +7.0V
300°C
(1) Stresses above those listed under
Absolute Maximum Ratings
may cause permanent
damage to the device. This is a stress rating only, and the functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Capacitance
T
A
= 25°C, f = 1.0MHz, V
CC
= 5V
Parameter
C
I/O(2)
C
IN(2)
Description
Input/Output Capacitance
Input Capacitance
8pF
6pF
Max
V
I/O
= 0V
V
I/O
= 0V
Test Condition
(2) This parameter is periodically sampled and not 100% tested.
DC Operating Conditions
T
A
= -40° to 85°C; Typical Values at 25°C
Symbol
V
CC
I
CC1
I
SB1
I
SB2
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
Parameters
Power Supply Voltage
Power Supply Current - Active
Min
4.5V
Typ
5.0
7mA
Max
5.5V
25mA
Test Condition
V
CC
= Maximum, CE Cycling at Minimum Cycle Time
I
I/O
= 0mA, CMOS Input Levels, OE = GND, WE = V
CC
V
CC
= Maximum, CE = V
IH
, TTL Input Levels, I
I/O
= 0mA
V
CC
= Maximum, CE = V
CC
, CMOS Input Levels, I
I/O
= 0mA
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Power Supply Current -
Standby (TTL)
Power Supply Current -
Standby (CMOS)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.4V
-1V
2.0V
20µA
600µA
50µA
10µA
10µA
0.8V
V
CC
+1V
0.4V
I
OL
= 4.2mA
I
OH
= -2.0mA
AC Conditions of Test
AC Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Levels
0 to 3 V
<10ns
1.5V
Equivalent AC Test Load Circuit
Test
+5V
919Ω
Output
100pF
497Ω
3
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