Radiometrix
Hartcran House, 231 Kenton Lane, Harrow, HA3 8RP, England
20 April 2007
Tel: +44 (0) 20 8909 9595, Fax: +44 (0) 20 8909 2233
RPC2A
UHF Radio Packet Controller
Modules: RPC2A-433-64: IC+BiM2A-433-64-S
IC’s:
RPC-000-DIL:
RPC-000-SO:
RPC-000-SS:
18 pin DIL IC
18 pin SO IC
20 pin SSOP IC
The RPC2A-433-64 is intelligent transceiver
modules, which enable a radio network/link to
be simply implemented between a number of
digital devices. The module combines a UHF
`
radio transceiver and a 64kbps packet
controller.
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•
•
•
•
•
•
•
•
•
•
•
Crystal controlled PLL FM circuitry for both Tx and Rx
Reliable 75 meter in-building range, 300m open ground
Built-in self-test / diagnostics / status LED’s
Complies with ETSI EN 300 220-3
Complies with ETSI EN 301 489-3
Single 5V supply @ < 27mA
64kbps half duplex
Free format packets of 1 - 27 bytes
Packet framing and error checking are user transparent
Collision avoidance (listen before transmit)
Direct interface to 5V CMOS logic
Power save mode
The RPC2A-module
I
NTRODUCTION
The RPC2A is an enhanced replacement for original RPC-433-40 transceiver. It is a self-contained plug-
on radio port which requires only a simple antenna, 5V supply and a byte-wide I/O port on a host
microcontroller (or bi-directional PC port).
The module provides all the RF circuits and processor intensive low level packet formatting and packet
recovery functions required to inter-connect an number of microcontrollers in a radio network.
A data packet of 1 to 27 bytes downloaded by a Host microcontroller into the RPC2A's packet buffer is
transmitted by the RPC2A’s transceiver and will "appear" in the receive buffer of all the RPC2A's within
radio range.
A data packet received by the RPC2A’s transceiver is decoded, stored in a packet buffer and the Host
microcontroller signalled that a valid packet is waiting to be uploaded.
transmit / receive
download
download
HOST
upload
figure 1: RPC2A + Host
µ
-controller
RPC2A
upload
HOST
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1. F
UNCTIONAL
D
ESCRIPTION
On receipt of a packet downloaded by the Host, the RPC2A will append to the packet: Preamble, start
byte and a error check code. The packet is then coded for security and mark:space balance and
transmitted through the BiM2A Transceiver as a 64kbps synchronous stream. One of four methods of
collision avoidance (listen before TX) may be user selected.
When not in transmit mode, the RPC2A continuously searches the radio noise for valid preamble. On
detection of preamble, the RPC2A synchronises to the in-coming data stream, decodes the data and
validates the check sum. The Host is then signalled that a valid packet is waiting to be unloaded. The
format of the packet is entirely of the users determination except the 1st byte (the Control Byte) which
must specify the packet type (control or data) and the packet size. A valid received packet is presented
back to the host in exactly the same form as it was given.
To preserve versatility, the RPC2A does not generate routing information (i.e.
source/ destination addresses) nor does it handshake packets. These network
specific functions should be performed by the host.
Additional features of the RPC2A include extensive diagnostic/debug functions for evaluation and
debugging of the radio and host driver software, a built in self test function and a sleep mode / wake-up
mechanism which may be programmed to reduce the average current to less than 100µA. The operating
parameters are fully programmable by the host and held in EEPROM, the host may also use the
EEPROM as a general purpose non-volatile store for addresses , routing information etc.
1.1 O
PERATING STATES
The RPC2A has four normal operating states:
•
•
•
•
I
DLE
/
SLEEP
HOST TRANSFER
TRANSMIT
RECEIVE
I
DLE
/S
LEEP
The
I
DLE
state is the quiescent/rest state of the RPC2A. In
I
DLE
the RPC2A enables the receiver
and continuously searches the radio noise for message preamble. If the power saving modes
have been enabled the RPC2A will pulse the receiver on, check for preamble and go back to
S
LEEP
if nothing is found. The 'ON' time is 5ms, OFF time is programmable in the RPC2A’s
EEPROM and can vary between 22ms and 2.9s. The TX Request line from the Host is constantly
monitored and will be acted upon if found active (low). A TX Request will immediately wake the
RPC2A up from
S
LEEP
mode.
H
OST
T
RANSFERS
If the host sets the TX Request line low a data transfer from the Host to the RPC2A will be
initiated. Similarly the RPC2A will pull RX Request low when it requires to transfer data to the
Host (this may polled or used to generate a Host interrupt).
The transfer protocol is fully asynchronous, i.e. the host may service another interrupt and then
continue with the RPC2A transfer. It is desirable that all transfers are completed quickly since
the radio transceiver is disabled until the Host <> RPC2A transfer is completed. Typically a fast
host can transfer a 27 byte packet to / from the RPC2A in under 1ms.
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T
RANSMIT
On receipt of a data packet from the host, the RPC2A will append to the packet - preamble,
frame sync byte and an error check sum. The packet is then coded for mark:space balance and
transmitted. A full 27 byte packet is transmitted in 8.1ms of TX air time (64kb/s + 5ms
preamble).
Collision avoidance (Listen Before Transmit-LBT) functions can be enabled to prevent loss of
packets.
Data packets may be sent with either normal or extended preamble. Extended preamble is used
if the remote RPC2A is in power save mode. Extended preamble length can be changed in the
EEPROM memory.
R
ECEIVE
On detection of preamble from the radio receiver, the RPC2A will phase lock, decode and error
check the incoming synchronous data stream and if successful. The data is then placed in a
buffer and the RX Request line is pulled low to signal to the host that a valid packet awaits to be
uploaded to the Host.
An in-coming data packet is presented back to the host in the same form as it was given.
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2 T
HE
H
OST
I
NTERFACE
2.1 S
IGNALS
It is recommended that the RPC2A be assigned to a byte wide bi-directional I/O port on the host
processor. The port must be such that the 4 data lines can be direction controlled without affecting the 4
handshake line.
pin
name
TXR
TXA
RXR
RXA
D0
D1
D2
D3
pin
number
6
7
8
9
2
3
4
5
pin
function
TX Request
TX Accept
RX Request
RX Accept
Data 0
Data 1
Data 2
Data 3
(4)
(5)
(6)
(7)
I/O
I/P
O/P
O/P
I/P
Bi-dir
Bi-dir
Bi-dir
Bi-dir
description
Data transfer request from HOST to
RPC2A
Data accept handshake back to HOST
Data transfer request from RPC2A to
HOST
Data accept handshake back to RPC2A
4 bit bi-directional data bus. Tri-state
between packet transfers, Driven on
receipt for Accept signal until packet
transfer is complete.
notes:
1. The 4 Handshake lines are active low
2. The 4 Data lines true data
3. Logic levels are 5V CMOS, see electrical specifications
4. Input pins have a weak pull-up internally
R
ESET
The Reset signal, may either be driven by the host (recommended) or pulled up to Vcc via a
suitable resistor (10kΩ). A reset aborts any transfers in progress and restarts the Packet
Controller.
H
OST DRIVEN RESET
Minimum low time: 1.0
µs,
after reset is released (returned high). The host should allow a delay
1ms after reset for the RPC2A to initialise itself
During this delay the host must hold TXR high (unless
D
IAGNOSTIC
M
ODES
are required) and
RXR signal should be ignored.
RPC2-433-64
D0
D1
D2
D3
Host
Processor
BiM2A-433-64
Transceiver
RESET
figure 5: Host to RPC2A connection
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