32Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
For Cisco
CMOS SRAM
Revision History
Rev .No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
History
Initial release with Preliminary.
Release to Final Data Sheet.
2.1. Add Low Power Version.
2.2. Add data retention charactoristic.
Draft Data
Aug. 1. 1998
Nov. 2. 1998
Feb. 25. 1999
Remark
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
Feburary 1999
KM68257E/EL, KM68257EI/ELI
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10, 12, 15ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 2mA(Max.)
0.6mA(Max.) L-ver. Only
Operating KM68257E/EL - 10 : 80mA(Max.)
KM68257E/EL - 12 : 80mA(Max.)
KM68257E/EL - 15 : 80mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention : L-Ver. only
• Standard Pin Configuration
KM68257EJ : 28-SOJ-300
KM68257ETG : 28-TSOP1-0813. 4F
For Cisco
CMOS SRAM
GENERAL DESCRIPTION
The KM68257E is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
KM68257E uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM68257E is packaged in
a 300mil 28-pin plastic SOJ or TSOP1 forward.
PIN CONFIGURATION
(Top View)
OE
A
11
A
9
A
8
A
13
WE
Vcc
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CS
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
Vss
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
TSOP1
ORDERING INFORMATION
KM68257E/EL -10/12/15
KM68257EI/ELI -10/12/15
Commercial Temp.
Industrial Temp.
FUNCTIONAL BLOCK DIAGRAM
A
14
1
28 Vcc
27 WE
26 A
13
25 A
8
24 A
9
23 A
11
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge-Circuit
A
12
2
A
7
3
A
6
4
A
5
5
Row Select
A
4
6
Memory Array
512 Rows
64x8 Columns
A
3
7
A
2
8
A
1
9
A
0
10
I/O
1
11
SOJ
22 OE
21 A
10
20 CS
19 I/O
8
18 I/O
7
17 I/O
6
16 I/O
5
15 I/O
4
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
I/O
2
12
I/O
3
13
Vss 14
PIN FUNCTION
A
9
A
10
A
11
A
12
A
13
A
14
Pin Name
CS
WE
OE
A
0
- A
14
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
-2-
Revision 2.0
Feburary 1999
KM68257E/EL, KM68257EI/ELI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
For Cisco
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5**
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0(Pulse Width≤7ns) for I≤20mA.
***
V
IH
(Max) = V
CC
+2.0V(Pulse Width≤7ns) for I≤20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C,V
CC
=5.0V±10% unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=0.1mA
Normal
L-Ver
10ns
12ns
15ns
Standby Current
I
SB
I
SB1
Min
-2
-2
-
-
-
-
-
-
-
2.4
-
Max
2
2
80
80
80
20
2
0.6
0.4
-
3.95
V
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1**
* The above parameters are also guaranteed at industrial temperature range.
** V
CC
=5.0V±5%, Temp.=25°C.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
* Capacitance is sampled and not 100% tested.
-3-
Revision 2.0
Feburary 1999
KM68257E/EL, KM68257EI/ELI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
For Cisco
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
+5V
480Ω
D
OUT
255Ω
30pF*
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
480Ω
D
OUT
255Ω
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM68257E/EL-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
KM68257E/EL-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
KM68257E/EL-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range
.
-4-
Revision 2.0
Feburary 1999
KM68257E/EL, KM68257EI/ELI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM68257E/EL-10
Min
10
8
0
8
8
10
0
0
5
0
0
Max
-
-
-
-
-
-
-
5
-
-
-
KM68257E/EL-12
Min
12
9
0
9
9
12
0
0
6
0
0
Max
-
-
-
-
-
-
-
6
-
-
-
For Cisco
CMOS SRAM
KM68257E/EL-15
Min
15
10
0
10
10
15
0
0
7
0
0
Max
-
-
-
-
-
-
-
7
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range
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