HY62UF16101C Series
64Kx16bit full CMOS SRAM
PRELIMINARY
DESCRIPTION
The HY62UF16101C is a high speed, super low
power and 1M bit full CMOS SRAM organized as
65,536 words by 16bit. The HY62UF16101C uses
high performance full CMOS process technology
and designed for high speed low power circuit
technology. It is particularly well suited for used in
high density low power system application. This
device has a data retention mode that guarantees
data to remain valid at a minimum power supply
voltage of 1.2V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup(LL/SL-part)
-. 1.2V(min) data retention
•
Standard pin configuration
-. 44 – TSOP II - 400mil
-. 48 - FBGA
Product
Voltage
Speed
No.
(V)
(ns)
HY62UF16101C
2.7~3.3 55/70/85
HY62UF16101C-I
2.7~3.3 55/70/85
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
Operation
Current/Icc(mA)
3
3
Standby Current(uA)
LL
SL
5
1
5
1
Temperature
(°C)
0~70
-40~85(I)
PIN CONNECTION
/LB
/OE A0
A1
A4
A6
A7
NC
A2
NC
A1~A7
A4
A3
A2
A1
A0
/CS
I/O1
I/O2
I/O3
I/O4
Vcc
GND
I/O5
I/O6
I/O7
I/O8
/WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/UB
/LB
I/O16
I/O15
I/O14
I/O13
GND
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
ADD INPUT
BUFFER
ROW
DECODER
I/O1
SENSE AMP
IO9 /UB A3
IO10 IO11 A5
Vss IO12 NC
Vcc IO13 NC
/CS IO1
IO2 IO3
IO4 Vcc
IO5 Vss
A14
A15
A8
A9
A10
A11
A12
A13
A0
/CS
/OE
/LB
/UB
/WE
DECODER
I/O8
BUFFER
ADD INPUT
BUFFER
PRE DECODER
MEMORY
ARRAY
64K x 16
WRITE DRIVER
I/O9
BLOCK
DECODER
IO15 IO14 A14 A15 IO6 IO7
IO16 NC
NC
A8
A12 A13 /WE IO8
A9
A10 A11 NC
ADD INPUT
BUFFER
I/O16
FBGA
TSOP¥
±
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Low Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Pin Name
I/O1~I/O16
A0~A15
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.7V~3.3V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jun. 00
Hyundai Semiconductor
HY62UF16101C Series
ORDERING INFORMATION
Part No.
HY62UF16101CLLT2
HY62UF16101CSLT2
HY62UF16101CLLT2-I
HY62UF16101CSLT2-I
HY62UF16101CLLF
HY62UF16101CSLF
HY62UF16101CLLF-I
HY62UF16101CSLF-I
Speed
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
Power
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
LL-part
SL-part
Temp.
Package
TSOP II (Standard)
TSOP II(Standard)
TSOP II(Standard)
TSOP II(Standard)
FBGA
FBGA
FBGA
FBGA
I
I
I
I
Note 1 Blank : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATING (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Lead Soldering Temperature & Time
Rating
-0.2 to 3.6
-0.2 to 4.6
0 to 70
-40 to 85
-55 to 150
1.0
260 10
Unit
V
V
°C
°C
°C
W
°C
sec
Remark
HY62UF16101C
HY62UF16101C-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
H
X
L
L
L
/WE
X
X
H
H
H
/OE
X
X
H
H
L
/LB
X
H
L
X
L
H
L
L
H
L
/UB
X
H
X
L
H
L
L
H
L
L
Mode
Deselected
Deselected
Output Disabled
Output Disabled
Read
I/O
I/O1~I/O8
High-Z
High-Z
High-Z
High-Z
D
OUT
Hi-Z
D
OUT
D
IN
Hi-Z
D
IN
I/O9~I/O16
High-Z
High-Z
High-Z
High-Z
Hi-Z
D
OUT
D
OUT
Hi-Z
D
IN
D
IN
Power
Stand by
Stand by
Active
Active
Active
L
L
X
Write
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care(V
IH
or V
IL)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the Upper byte, I/O 9 -I/O 16.
Rev.02 /Jun. 00
2
HY62UF16101C Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
2.2
-0.3
(1)
Typ.
3.0
0
-
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
2. Undershoots are sampled and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.3V, T
A
= 0°C to 70°C / -40°C to 85°C (I)
Sym
Parameter
Test Condition
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL,
/
UB
=
V
IH
and /LB = V
IH
Icc
Operating Power Supply
/CS = V
IL
, V
IN
= V
IH
or V
IL,
Current
I
I/O =
0mA
I
CC1
Average Operating Current
/CS < 0.2V,
1us
Cycle
Time,100% Duty, I
I/O =
0mA,
V
IN
< 0.2V
/CS = V
IL,
V
IN
= V
IH
or V
IL
Cycle Time = Min. 100% Duty
I
I/O =
0mA
I
SB
TTL Standby Current
/CS = V
IH
or /CS = V
IL,
(TTL Input)
/UB,/LB = V
IH
I
SB1
Standby Current
/CS > Vcc - 0.2V
SL
(CMOS Input)
LL
V
OL
Output Low Voltage
I
OL
= 2.1mA
V
OH
Output High Voltage
I
OH =
-1.0mA
Note : 1.Typical values are at Vcc = 3.0V, T
A
= 25°C
2.Typical values are sampled and not 100% tested.
Min.
-1
-1
Typ.
-
-
Max.
1
1
Unit
uA
uA
-
-
-
-
3
5
mA
mA
-
-
45
mA
-
-
-
2.4
-
-
0.5
-
-
0.5
1
5
0.4
-
mA
uA
uA
V
V
CAPACITANCE
(Temp = 25¡
É
f= 1.0MHz)
,
Symbol
Parameter
C
IN
Input Capacitance(Add, /CS, /UB, /LB, /WE, /OE)
C
OUT
Output Capacitance(I/O)
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Rev.02 /Jun. 00
3
HY62UF16101C Series
AC CHARACTERISTICS
Vcc = 2.7~3.3V, T
A
= 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
-55
-70
Parameter
# Symbol
Min.
Max. Min.
Max.
READ CYCLE
1
tRC
Read Cycle Time
55
-
70
-
2
tAA
Address Access Time
-
55
-
70
3
tACS
Chip Select Access Time
-
55
-
70
4
tOE
Output Enable to Output Valid
-
35
-
40
5
tBA
/LB, /UB Access Time
-
55
-
70
6
tCLZ
Chip Select to Output in Low Z
10
-
10
-
7
tOLZ
Output Enable to Output in Low Z
5
-
5
-
8
tBLZ
/LB, /UB Enable to Output in Low Z
5
-
5
-
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
10 tOHZ
Out Disable to Output in High Z
0
30
0
30
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
12 tOH
Output Hold from Address Change
10
-
10
-
WRITE CYCLE
13 tWC
Write Cycle Time
55
-
70
-
14 tCW
Chip Selection to End of Write
50
-
60
-
15 tAW
Address Valid to End of Write
50
-
60
-
16 tBW
/LB, /UB Valid to End of Write
50
-
60
-
17 tAS
Address Set-up Time
0
-
0
-
18 tWP
Write Pulse Width
45
-
50
-
19 tWR
Write Recovery Time
0
-
0
-
20 tWHZ
Write to Output in High Z
0
20
0
25
21 tDW
Data to Write Time Overlap
25
-
30
-
22 tDH
Data Hold from Write Time
0
-
0
-
23 tOW
Output Active from End of Write
5
-
5
-
-85
Min
Max.
85
-
-
-
-
10
5
5
0
0
0
10
85
70
70
70
0
55
0
0
35
0
5
-
85
85
45
85
-
-
-
30
30
30
-
-
-
-
-
-
-
-
30
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM=2.8V
1029 Ohm
D
OUT
CL(1)
1728 Ohm
Note
1. Including jig and scope capacitance
Rev.02 /Jun. 00
4
HY62UF16101C Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tACS
/CS
tCHZ
(3)
tBA
/UB ,/ LB
tOE
tOLZ
(3)
tBLZ
(3)
tCLZ
(3)
Data Valid
tBHZ
(3)
tOH
/OE
tOHZ
(3)
Data
Out
High-Z
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
Data
Out
Data Valid
tCHZ(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1
are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.02 /Jun. 00
5
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