HN29V256A1B (×8)
×
HN29V256A0B (×16)
×
256M superAND Flash Memory
(with internal sector management)
REJ03C0033-0002Z
Preliminary
Rev.0.02
Jan.30.2004
Description
The HN29V256A1B and HN29V256A0B Series is a CMOS flash memory, which uses cost effective and
high performance AND type multi-level memory cell technology. Current AND flash memory requires us
to support complicated operations such as sector management for defect sector and error check correction.
But this series doesn’t need such operations. Beside it supports wear leveling function, which is sector
replacement function in case of that certain sector, reaches certain erase/write times. And power-on-auto-
read function is available. It enables to read the data of the sectors from sector address 0 to 3 (8k byte)
without command and address data input when power is on.
Note: This product is authorized for using consumer application such as cellular phone,
therefore, please contact Renesas Technology’s sales office before using other applications.
Features
•
On-board single power supply (V
CC
): V
CC
= 2.7 V to 3.6 V
•
Operating temperature range: Ta = 0 to +70°C
•
Program/erase, rewrite endurance
10 times
5
•
Access time
First access
90
µs
(typ) (×8/×16)
Serial read cycle
50 ns (min) (×8/×16)
Maximum transfer rate (sequential read)
20.0 Mbyte/s (×8)
40.0 Mbyte/s (×16)
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology's Sales Dept. regarding specifications.
Rev.0.02, Jan.30.2004, page 1 of 53
HN29V256A1B/A0B Series
•
Program time
1.2 ms (typ) /4096 byte (×8/×16)
•
Erase time
2.0 ms (typ) /8192 byte (×8/×16)
•
Rewrite time
4.5 ms (typ) /4096 byte (×8/×16)
•
Low power dissipation
Standby current
I
CCS1
= 1 mA (max)
I
CCS2
= 50
µA
(max) (CMOS level)
I
CCS3
= 10
µA
(max) (deep standby)
Serial read operation current
I
CC1
= 30 mA (max)
Program/erase/rewrite operation current
I
CC2/3/4
= 40 mA (max) (program/erase/rewrite)
•
Sector management
Following functions are build-in flash memory component.
Sector management:
If certain sector had been damaged, it would be replaced by the spare sector automatically.
Always 100% of sector number are available up to 10 erase/write cycles per device.
Error check and correction:
ECC code is generated at the time of programming, and data error is checked at the time of read
operation. If data error occurs, the data will be corrected automatically.
(ECC: 1-byte error correction, 2-byte error detection per 512byte page)
Wear leveling:
To avoid erase/program/rewrite operation converge on the particular physical sector, the number of
erase/program/rewrite operation will be leveled automatically by changing internal logical sector
address.
•
Package line up
CSP: CSP 95-bump (TBP-95V)
5
Ordering Information
Type No.
HN29V256A1BBP-30
HN29V256A0BBP-30
Organization
×8
×16
Package
10.0
×
11.50 mm , 95-bump
0.8 mm ball pitch CSP (TBP-95V)
Lead free
2
Rev.0.02, Jan.30.2004, page 2 of 53
HN29V256A1B/A0B Series
Pin Arrangement
95-bump CSP
95-bump CSP
1
A
B
C
D
E
F
G
H
J
K
L
M
DU
DU
DU
DU
2
DU
DU
DU
DU
DU
3
4
5
6
7
8
9
10
11
DU
DU
12
DU
DU
DU
DU
DU
DU
R/
B
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
PRE
I/O3
DU
DU
DU
DU
I/O15
DU
V
SS
I/O8
DU
I/O7
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
MRES
WE
V
SS
I/O13 I/O6
I/O5
DU
I/O1
DU
DU
DU
I/O11
I/O9
DU
V
SS
I/O14 I/O16
DU
V
CC
RES
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
WP
DU
CLE
ALE
I/O4 I/O12
I/O2 I/O10
DU
DU
RE
CE
(TOP View)
Rev.0.02, Jan.30.2004, page 3 of 53
HN29V256A1B/A0B Series
Pin Description
Name
I/O1 to I/O8
I/O9 to I/O16
CLE
ALE
CE
RE
WE
WP
R/B
PRE
MRES
RES
V
CC
V
SS
DU
Note:
Description
Command, address, data input/output
Data input/output (×8 device: DU)
Command latch enable
Address latch enable
Chip enable
Read enable
Write enable
Write protect
Ready/busy
Power on auto read enable
Master reset output
Reset
Power supply
Ground
Don’t use
1. All V
SS
pins should be connected respectively.
Rev.0.02, Jan.30.2004, page 4 of 53
HN29V256A1B/A0B Series
Pin Function
Chip enable:
CE
CE
is for selecting a chip and making the device in the active state.
During command waiting state,
CE
= H makes the device standby state.
During command execution such as erase, program and rewrite,
CE
= H can’t stop command operation
itself.
Read enable:
RE
RE
is output enable pin and also controls read timing. Clocking
RE
increments the internal address and
reads out each data.
Write enable:
WE
Commands, address, and program data are latched into the device at the rising edge of
WE.
Command latch enable: CLE
CLE specifies the command data. When CLE = H, data on I/O bus will be recognized as the command
data.
The command data is latched on the rising edge of
WE
with CLE = H.
Address latch enable: ALE
ALE specifies the address data. When ALE = H, data on I/O bus will be recognized as the address data.
The address data is latched on the rising edge of
WE
with ALE = H.
Write protect:
WP
WP
= L disables erase, program and rewrite operation.
Ready/busy R/B
busy: B
busy
R/B is the output signal. It shows the internal status of the device to be ready or busy.
It is an open-drain signal and should be pulled up to V
CC
via suitable resistance.
Rev.0.02, Jan.30.2004, page 5 of 53
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
